(V = +3 V or 5 V, REF IN(+) = +1.225 V with V = 3 V and +2.5 V
with VDD = 5 V; REF IN(–) = GND; MCLK IN = 2.4576 MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
AD7705/AD7706–SPECIFICATIONS
DD
DD
Parameter
B Version1
Units
Conditions/Comments
STATIC PERFORMANCE
No Missing Codes
16
Bits min
Guaranteed by Design. Filter Notch < 60 Hz
Depends on Filter Cutoffs and Selected Gain
Filter Notch < 60 Hz. Typically ±0.0003%
Output Noise
See Tables I and III
Integral Nonlinearity2
Unipolar Offset Error
Unipolar Offset Drift4
Bipolar Zero Error
Bipolar Zero Drift4
±0.003
See Note 3
0.5
See Note 3
0.5
0.1
See Note 3
0.5
See Note 3
0.5
±0.003
1
0.6
% of FSR max
µV/°C typ
µV/°C typ
µV/°C typ
For Gains 1, 2 and 4
For Gains 8, 16, 32, 64 and 128
Positive Full-Scale Error5
Full-Scale Drift4, 6
µV/°C typ
Gain Error7
Gain Drift4, 8
ppm of FSR/°C typ
% of FSR typ
µV/°C typ
Bipolar Negative Full-Scale Error2
Bipolar Negative Full-Scale Drift4
Typically ±0.001%
For Gains of 1 to 4
For Gains of 8 to 128
µV/°C typ
ANALOG INPUTS/REFERENCE INPUTS
Specifications for AIN and REF IN Unless Noted
Input Common-Mode Rejection (CMR)2
VDD = 5 V
Gain = 1
Gain = 2
Gain = 4
Gain = 8v128
96
dB typ
dB typ
dB typ
dB typ
105
110
130
V
DD = 3 V
Gain = 1
Gain = 2
Gain = 4
105
110
120
130
98
98
150
150
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
V min to V max
V min
V max
V min
V max
nA max
pF max
nom
Gain = 8v128
Normal-Mode 50 Hz Rejection2
For Filter Notches of 25 Hz, 50 Hz, ±0.02 × fNOTCH
For Filter Notches of 20 Hz, 60 Hz, ±0.02 × fNOTCH
For Filter Notches of 25 Hz, 50 Hz, ±0.02 × fNOTCH
For Filter Notches of 20 Hz, 60 Hz, ±0.02 × fNOTCH
Normal-Mode 60 Hz Rejection2
Common-Mode 50 Hz Rejection2
Common-Mode 60 Hz Rejection2
Absolute/Common-Mode REF IN Voltage2
Absolute/Common-Mode AIN Voltage2, 9
GND to VDD
GND – 30 mV
VDD + 30 mV
GND + 50 mV
VDD – 1.5 V
1
BUF Bit of Setup Register = 0
BUF Bit of Setup Register = 1
Absolute/Common-Mode AIN Voltage2, 9
AIN DC Input Current2
AIN Sampling Capacitance2
AIN Differential Voltage Range10
10
0 to +VREF/GAIN11
±VREF/GAIN
GAIN × fCLKIN/64
fCLKIN/8
Unipolar Input Range (B/U Bit of Setup Register = 1)
Bipolar Input Range (B/U Bit of Setup Register = 0)
For Gains of 1 to 4
nom
AIN Input Sampling Rate, fS
For Gains of 8 to 128
Reference Input Range
REF IN(+) – REF IN(–) Voltage
1/1.75
1/3.5
V min/max
V min/max
VDD = 2.7 V to 3.3 V. VREF = 1.225 ± 1% for Specified
Performance
VDD = 4.75 V to 5.25 V. VREF = 2.5 ± 1% for Specified
Performance
REF IN(+) – REF IN(–) Voltage
REF IN Input Sampling Rate, fS
fCLKIN/64
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
MCLK
±1
±10
µA max
µA max
Typically ±20 nA
Typically ±2 µA
All Inputs Except SCLK and MCLK IN
VINL, Input Low Voltage
0.8
0.4
2.0
V max
V max
V min
VDD = 5 V
VDD = 3 V
VDD = 3 V and 5 V
VDD = 5 V NOMINAL
VINH, Input High Voltage
SCLK Only (Schmitt Triggered Input)
VT+
VT–
VT+ – VT–
1.4/3
0.8/1.4
0.4/0.8
V min/V max
V min/V max
V min/V max
SCLK Only (Schmitt Triggered Input)
VT+
VT–
VT+ – VT–
VDD = 3 V NOMINAL
1/2.5
0.4/1.1
0.375/0.8
V min/V max
V min/V max
V min/V max
MCLK IN Only
VINL, Input Low Voltage
VINH, Input High Voltage
MCLK IN Only
VINL, Input Low Voltage
VINH, Input High Voltage
VDD = 5 V NOMINAL
VDD = 3 V NOMINAL
0.8
3.5
V max
V min
0.4
2.5
V max
V min
–2–
REV. A
ADI [ ADI ]
