AD7705/AD7706
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.25 V; GND = 0 V; fCLKIN = 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = VDD, unless otherwise noted.
Table 2. Timing Characteristics1, 2
Limit at TMIN, TMAX
(B Version)
Parameter
Unit
Conditions/Comments
3, 4
fCLKIN
400
2.5
0.4 ꢀ tCLKIN
0.4 ꢀ tCLKIN
500 ꢀ tCLKIN
100
kHz min
MHz max
ns min
ns min
ns nom
ns min
Master clock frequency (crystal oscillator or externally supplied)
For specified performance
Master clock input low time, tCLKIN = 1/fCLKIN
Master clock input high time
DRDY high time
tCLKIN LO
tCLKIN HI
t1
t2
RESET pulse width
Read Operation
t3
t4
0
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns max
DRDY to CS setup time
120
0
80
100
100
100
0
CS falling edge to SCLK rising edge setup time
SCLK falling edge to data valid delay
VDD = 5 V
VDD = 3.0 V
SCLK high pulse width
5
t5
t6
t7
t8
SCLK low pulse width
CS rising edge to SCLK rising edge hold time
Bus relinquish time after SCLK rising edge
VDD = 5 V
VDD = 3.0 V
SCLK falling edge to DRDY high7
6
t9
10
60
100
100
t10
Write Operation
t11
t12
t13
t14
t15
t16
120
30
20
100
100
0
ns min
ns min
ns min
ns min
ns min
ns min
CS falling edge to SCLK rising edge setup time
Data valid to SCLK rising edge setup time
Data valid to SCLK rising edge hold time
SCLK high pulse width
SCLK low pulse width
CS rising edge to SCLK rising edge hold time
1 Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 See Figure 19 and Figure 20.
3 The fCLKIN duty cycle range is 45% to 55%. fCLKIN must be supplied whenever the AD7705/AD7706 are not in standby mode. If no clock is present, the devices can draw
higher current than specified, and possibly become uncalibrated.
4 The AD7705/AD7706 are production tested with fCLKIN at 2.4576 MHz (1 MHz for some IDD tests). They are guaranteed by characterization to operate at 400 kHz.
5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
7 DRDY
DRDY
returns high upon completion of the first read from the device after an output update. The same data can be reread while
is high, but care should be
taken that subsequent reads do not occur close to the next output update.
I
(800μA AT V = 5V
DD
SINK
100μA AT V = 3V)
DD
TO OUTPUT
PIN
1.6V
50pF
I
(200μA AT V = 5V
DD
100mA AT V = 3V)
DD
SOURCE
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
Rev. C | Page 8 of 44
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