AD7705/AD7706
AD7705/AD7706-to-8051 Interface
AD7705/AD7706-to-ADSP-2103/ADSP-2105 Interface
An interface circuit between the AD7705/AD7706 and the 8XC51
microcontroller is shown in Figure 23. The diagram shows the
Figure 24 shows an interface between the AD7705/AD7706 and
the ADSP-2103/ADSP-2105 DSP processor. In the interface
CS
minimum number of interface connections with
on the
DRDY
shown, the
bit of the communication register is monitored
AD7705/AD7706 hardwired low. In the case of the 8XC51
interface, the minimum number of interconnects is two. In this
to determine when the data register is updated. The alternative
scheme is to use an interrupt-driven system, in which case the
DRDY
scheme, the
bit of the communication register is monitored
DRDY
IRQ2
output is connected to the
ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105
RFS TFS
input of the ADSP-2103/
to determine when the data register is updated. The alternative
scheme, which increases the number of interface lines to three,
is set up for alternate framing mode. The
and
pins of
DRDY
is to monitor the
DRDY
output line from the AD7705/AD7706.
DRDY
line can be done in two ways. First,
the ADSP-2103/ADSP-2105 are configured as active low outputs,
and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is
Monitoring the
can be connected to a 8XC51 port bit (such as P1.0) that is
configured as an input. This port bit is then polled to determine
CS
configured as an output. The
for the AD7705/AD7706 is
RFS TFS
active when either the
or
outputs from the ADSP-2103/
DRDY
the status of
. The second scheme is to use an interrupt-
DRDY
ADSP-2105 are active. The serial clock rate on the ADSP-2103/
ADSP-2105 should be limited to 3 MHz to ensure correct
operation with the AD7705/AD7706.
driven system, in which case the
output is connected to
INT1
the
input of the 8XC51. For interfaces that require control
CS
of the
input on the AD7705/AD7706, a port bit of the 8XC51
CODE FOR SETTING UP THE AD7705/AD7706
(such as P1.1) that is configured as an output can be used to
CS
The following section shows a set of read and write routines in
C code for interfacing the 68HC11 microcontroller to the AD7705.
The sample program sets up the various registers on the AD7705
and reads 1000 samples from one channel into the 68HC11. The
setup conditions on the part are the same as those outlined for the
drive the
input. The 8XC51 is configured in Mode 0 serial
interface mode. Its serial interface contains a single data line.
As a result, the DOUT and DIN pins of the AD7705/
AD7706 should be connected together with a 10 kΩ pull-up
resistor. The serial clock on the 8XC51 idles high between data
transfers. During a write operation, the 8XC51 outputs the LSB
first. Because the AD7705/AD7706 expect the MSB first, the
data must be rearranged before being written to the output
serial register. Similarly, during a read operation, the AD7705/
AD7706 output the MSB first, and the 8XC51 expects the LSB
first. Therefore, the data read into the serial buffer must be
rearranged before the correct data-word from the AD7705/
AD7706 is available in the accumulator.
DRDY
flowchart of Figure 21. In the example code given here, the
output is polled to determine if a new valid word is available in
the data register. The same sequence is applicable for the AD7706.
The sequence of events in this program are as follows:
1. Write to the communication register, selecting Channel 1
as the active channel and setting the next operation to be a
write to the clock register.
AD7705/AD7706
2. Write to the clock register, setting the CLKDIV bit, which
divides the external clock internally by two. This assumes
that the external crystal is 4.9512 MHz. The update rate is
selected to be 50 Hz.
V
DD
ADSP-2103/
ADSP-2105
RESET
CS
RFS
3. Write to the communication register selecting Channel 1 as
the active channel and setting the next operation to be a
write to the setup register.
TFS
DOUT
DIN
DR
4. Write to the setup register, setting the gain to 1, setting
bipolar mode, buffer off, clearing the filter
DT
synchronization, and initiating a self-calibration.
SCLK
SCLK
DRDY
5. Poll the
output.
6. Read the data from the data register.
Figure 24. AD7705/AD7706-to-ADSP-2103/ADSP-2105 Interface
7. Repeat Steps 5 and 6 (loop) until the specified number of
samples has been taken from the selected channel.
Rev. C | Page 35 of 44
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