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AD7606BSTZ-6RL 参数 Datasheet PDF下载

AD7606BSTZ-6RL图片预览
型号: AD7606BSTZ-6RL
PDF下载: 下载PDF文件 查看货源
内容描述: 8 / 6 / 4通道DAS,内置16位,双极性输入,同步采样ADC [8-/6-/4-Channel DAS with 16-Bit,Bipolar Input,Simultaneous Sampling ADC]
分类和应用: 转换器模数转换器
文件页数/大小: 36 页 / 781 K
品牌: ADI [ ADI ]
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AD7606/AD7606-6/AD7606-4  
DIGITAL INTERFACE  
The AD7606/AD7606-6/AD7606-4 provide three interface  
options: a parallel interface, a high speed serial interface, and  
a parallel byte interface. The required interface mode is selected  
RD  
signal is logic low, it enables the data conversion  
result from each channel to be transferred to the digital host  
(DSP, FPGA).  
When the  
PAR  
via the  
/SER/BYTE SEL and DB15/BYTE SEL pins.  
When there is only one AD7606/AD7606-6/AD7606-4 in  
a system/board and it does not share the parallel bus, data can  
be read using just one control signal from the digital host. The  
Table 8. Interface Mode Selection  
PAR/SER/BYTE SEꢀ  
DB1±  
Interface Mode  
CS  
RD  
and  
In this case, the data bus comes out of three-state on the falling  
CS RD CS RD  
signal allows the data  
signals can be tied together, as shown in Figure 5.  
0
1
1
0
0
1
Parallel interface mode  
Serial interface mode  
Parallel byte interface mode  
edge of  
/
. The combined  
and  
to be clocked out of the AD7606/AD7606-6/AD7606-4 and to  
Operation of the interface modes is discussed in the following  
sections.  
CS  
be read by the digital host. In this case,  
data transfer of each data channel.  
is used to frame the  
PARAꢀꢀEꢀ INTERFACE (PAR/SER/BYTE SEꢀ = 0)  
PARAꢀꢀEꢀ BYTE (PAR/SER/BYTE SEꢀ = 1, DB1± = 1)  
Data can be read from the AD7606/AD7606-6/AD7606-4 via  
Parallel byte interface mode operates much like the parallel  
interface mode, except that each channel conversion result is read  
CS  
RD  
the parallel data bus with standard  
PAR  
and  
signals. To read the  
data over the parallel bus, the  
CS RD  
/SER/BYTE SEL pin should  
input signals are internally gated to  
RD  
out in two 8-bit transfers. Therefore, 16  
to read all eight conversion results from the AD7606. For the  
RD  
pulses are required  
be tied low. The  
and  
enable the conversion result onto the data bus. The data lines,  
CS  
AD7606-6, 12  
pulses are required; and on the AD7606-4,  
pulses are required to read all the channel results.  
To configure the AD7606/AD76706-6/AD7606-4 to operate in  
PAR  
DB15 to DB0, leave their high impedance state when both  
RD  
RD  
eight  
and  
are logic low.  
parallel byte mode, the  
/SER/BYTE SEL and BYTE SEL/  
AD7606  
INTERRUPT  
BUSY 14  
DB15 pins should be tied to logic high (see Table 8). In parallel  
byte mode, DB[7:0] are used to transfer the data to the digital  
host. DB0 is the LSB of the data transfer, and DB7 is the MSB of  
the data transfer. In parallel byte mode, DB14 acts as an HBEN  
pin. When DB14/HBEN is tied to logic high, the most  
significant byte (MSB) of the conversion result is output first,  
followed by the LSB of the conversion result. When DB14 is tied  
to logic low, the LSB of the conversion result is output first,  
followed by the MSB of the conversion result. The FRSTDATA  
pin remains high until the entire 16 bits of the conversion result  
from V1 are read from the AD7606/AD7606-6/AD7606-4.  
13  
12  
CS  
RD/SCLK  
DB[15:0]  
DIGITAL  
HOST  
[33:24]  
[22:16]  
Figure 45. AD7606 Interface Diagram—One AD7606 Using the Parallel Bus,  
CS RD  
with and  
Shorted Together  
CS  
CS  
CS  
The rising edge of the  
the falling edge of the  
high impedance state.  
input signal three-states the bus, and  
input signal takes the bus out of the  
is the control signal that enables the  
data lines; it is the function that allows multiple AD7606/  
AD7606-6/ AD7606-4 devices to share the same parallel  
data bus.  
SERIAꢀ INTERFACE (PAR/SER/BYTE SEꢀ = 1)  
To read data back from the AD7606 over the serial interface, the  
CS  
RD  
signal  
The  
signal can be permanently tied low, and the  
PAR  
CS  
/SER/BYTE SEL pin must be tied high. The  
and SCLK  
can be used to access the conversion results as shown in Figure 4.  
A read operation of new data can take place after the BUSY  
signal goes low (see Figure 2); or, alternatively, a read operation  
of data from the previous conversion process can take place  
while BUSY is high (see Figure 3).  
signals are used to transfer data from the AD7606. The AD7606/  
AD7606-6/AD7606-4 have two serial data output pins, DOUTA  
and DOUTB. Data can be read back from the AD7606/AD76706-  
6/AD7606-4 using one or both of these DOUT lines. For the  
AD7606, conversion results from Channel V1 to Channel V4  
first appear on DOUTA, and conversion results from Channel V5  
to Channel V8 first appear on DOUTB. For the AD7606-6,  
conversion results from Channel V1 to Channel V3 first appear  
on DOUTA, and conversion results from Channel V4 to Channel  
V6 first appear on DOUTB. For the AD7606-4, conversion results  
from Channel V1 and Channel V2 first appear on DOUTA, and  
conversion results from Channels V3 and Channel V4 first  
appear on DOUTB.  
RD  
The  
results register. Applying a sequence of  
of the AD7606/AD7606-6/AD7606-4 clocks the conversion  
pin is used to read data from the output conversion  
RD RD  
pulses to the  
pin  
results out from each channel onto the Parallel Bus DB[15:0] in  
RD  
ascending order. The first  
falling edge after BUSY goes low  
RD  
clocks out the conversion result from Channel V1. The next  
falling edge updates the bus with the V2 conversion result, and so  
RD  
on. On the AD7606, the eighth falling edge of  
conversion result for Channel V8.  
clocks out the  
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