AD7606/AD7606-6/AD7606-4
ꢀimit at TMIN, TMAX
Parameter
Min
Typ
Max
Unit Description
Delay from CS until DB[15:0] three-state disabled
t13
16
20
25
30
ns
ns
ns
ns
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
Data access time after RD falling edge
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
4
t14
16
21
25
32
ns
ns
ns
ns
ns
ns
ns
t15
t16
t17
6
6
Data hold time after RD falling edge
CS to DB[15:0] hold time
Delay from CS rising edge to DB[15:0] three-state enabled
22
SERIAL READ OPERATION
fSCLK
Frequency of serial read clock
23.5
17
14.5
11.5
MHz VDRIVE above 4.75 V
MHz VDRIVE above 3.3 V
MHz VDRIVE above 2.7 V
MHz VDRIVE above 2.3 V
t18
Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS
until MSB valid
15
20
30
ns
ns
ns
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE = 2.3 V to 2.7 V
Data access time after SCLK rising edge
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
SCLK low pulse width
4
t19
17
23
27
34
ns
ns
ns
ns
ns
ns
t20
t21
t22
t23
0.4 tSCLK
0.4 tSCLK
7
SCLK high pulse width
SCLK rising edge to DOUTA/DOUTB valid hold time
CS rising edge to DOUTA/DOUTB three-state enabled
22
ns
FRSTDATA OPERATION
t24
Delay from CS falling edge until FRSTDATA three-state disabled
15
20
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
t25
CS
falling edge until FRSTDATA high, serial mode
Delay from
15
20
25
30
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
t26
Delay from RD falling edge to FRSTDATA high
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
16
20
25
30
ns
ns
ns
ns
Rev. 0 | Page 8 of 36
ADI [ ADI ]
