AD7606/AD7606-6/AD7606-4
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted.1
Table 3.
ꢀimit at TMIN, TMAX
Parameter
Min
Typ
Max
Unit Description
PARALLEL/SERIAL/BYTE MODE
tCYCLE
1/throughput rate
Parallel mode, reading during or after conversion; or serial mode: VDRIVE =
5
μs
4.75 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines
Serial mode reading during conversion; VDRIVE = 3.3 V
Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines
Conversion time
5
μs
μs
9.7
2
tCONV
3.45
4
3
2
4.15
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
Oversampling off; AD7606
Oversampling off; AD7606-6
Oversampling off; AD7606-4
Oversampling by 2; AD7606
Oversampling by 4; AD7606
Oversampling by 8; AD7606
Oversampling by 16; AD7606
Oversampling by 32; AD7606
7.87
16.05
33
66
133
257
9.1
18.8
39
78
158
315
100
Oversampling by 64; AD7606
STBY rising edge to CONVST x rising edge; power-up time from
standby mode
tWAKE-UP STANDBY
tWAKE-UP SHUTDOWN
Internal Reference
30
13
ms
ms
STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
External Reference
tRESET
tOS_SETUP
tOS_HOLD
t1
t2
t3
t4
50
20
20
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
RESET high pulse width
BUSY to OS x pin setup time
BUSY to OS x pin hold time
CONVST x high to BUSY high
Minimum CONVST x low pulse
Minimum CONVST x high pulse
BUSY falling edge to CS falling edge setup time
40
25
25
0
3
t5
0.5
25
Maximum delay allowed between CONVST A, CONVST B rising edges
Maximum time between last CS rising edge and BUSY falling edge
Minimum delay between RESET low to CONVST x high
t6
t7
25
PARALLEL/BYTE READ
OPERATION
t8
0
0
ns
ns
CS to RD setup time
t9
CS to RD hold time
t10
RD low pulse width
16
21
25
32
15
22
ns
ns
ns
ns
ns
ns
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
RD high pulse width
CS high pulse width (see Figure 5); CS and RD linked
t11
t12
Rev. 0 | Page 7 of 36
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