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AD7606BSTZ 参数 Datasheet PDF下载

AD7606BSTZ图片预览
型号: AD7606BSTZ
PDF下载: 下载PDF文件 查看货源
内容描述: 8 / 6 / 4通道DAS,内置16位,双极性输入,同步采样ADC [8-/6-/4-Channel DAS with 16-Bit,Bipolar Input,Simultaneous Sampling ADC]
分类和应用: 转换器模数转换器PC
文件页数/大小: 36 页 / 781 K
品牌: ADI [ ADI ]
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AD7606/AD7606-6/AD7606-4  
CS  
CS  
takes the bus out of three-state and clocks  
The falling edge takes the data output lines, DOUTA and DOUTB,  
The falling edge of  
out the MSB of the 16-bit conversion result. This MSB is valid  
CS  
out of three-state and clocks out the MSB of the conversion  
result. The rising edge of SCLK clocks all subsequent data bits  
on the first falling edge of the SCLK after the  
falling edge.  
CS  
onto the serial data outputs, DOUTA and DOUTB. The  
input  
The subsequent 15 data bits are clocked out of the AD7606/  
AD7606-6/AD7606-4 on the SCLK rising edge. Data is valid on  
the SCLK falling edge. To access each conversion result, 16 clock  
cycles must be provided to the AD7606/AD7606-6/AD7606-4.  
can be held low for the entire serial read operation, or it can be  
pulsed to frame each channel read of 16 SCLK cycles. Figure 46  
shows a read of eight simultaneous conversion results using two  
D
OUT lines on the AD7606. In this case, a 64 SCLK transfer is used  
The FRSTDATA output signal indicates when the first channel,  
CS  
to access data from the AD7606, and is held low to frame the  
entire 64 SCLK cycles. Data can also be clocked out using just  
one DOUT line, in which case it is recommended that DOUTA be  
used to access all conversion data because the channel data is  
output in ascending order. For the AD7606 to access all eight  
conversion results on one DOUT line, a total of 128 SCLK cycles  
CS  
V1, is being read back. When the input is high, the FRSTDATA  
output pin is in three-state. In serial mode, the falling edge of  
CS  
takes FRSTDATA out of three-state and sets the FRSTDATA  
pin high, indicating that the result from V1 is available on the  
DOUTA output data line. The FRSTDATA output returns to  
a logic low following the 16th SCLK falling edge. If all channels  
are read on DOUTB, the FRSTDATA output does not go high when  
V1 is being output on this serial data output pin. It goes high  
only when V1 is available on DOUTA (and this is when V5 is  
available on DOUTB for the AD7606).  
CS  
is required. These 128 SCLK cycles can be framed by one  
signal, or each group of 16 SCLK cycles can be individually  
CS  
framed by the  
signal. The disadvantage of using just one  
DOUT line is that the throughput rate is reduced if reading occurs  
after conversion. The unused DOUT line should be left unconnected  
in serial mode. For the AD7606, if DOUTB is to be used as a single  
READING DURING CONVERSION  
Data can be read from the AD7606/AD7606-6/AD7606-4 while  
BUSY is high and the conversions are in progress. This has little  
effect on the performance of the converter, and it allows a faster  
throughput rate to be achieved. A parallel, parallel byte, or serial  
read can be performed during conversions and when oversampling  
may or may not be in use. Figure 3 shows the timing diagram for  
reading while BUSY is high in parallel or serial mode. Reading  
during conversions allows the full throughput rate to be achieved  
when using the serial interface with VDRIVE above 4.75 V.  
D
OUT line, the channel results are output in the following order:  
V5, V6, V7, V8, V1, V2, V3, and V4; however, the FRSTDATA  
indicator returns low after V5 is read on DOUTB. For the AD7606-6  
and the AD7606-4, if DOUTB is to be used as a single DOUT line,  
the channel results are output in the following order: V4, V5, V6,  
V1, V2, and V3 for the AD7606-6; and V3, V4, V1, and V2 for  
the AD7606-4.  
Figure 6 shows the timing diagram for reading one channel of  
CS  
data, framed by the  
AD7606-4 in serial mode. The SCLK input signal provides the  
CS  
signal, from the AD7606/AD7606-6/  
Data can be read from the AD7606 at any time other than on  
the falling edge of BUSY because this is when the output data  
registers are updated with the new conversion data. Time t6, as  
outlined in Table 3, should be observed in this condition.  
clock source for the serial read operation. The  
goes low to  
access the data from the AD7606/AD7606-6/AD7606-4.  
CS  
64  
SCLK  
D
D
A
B
V1  
V5  
V2  
V6  
V3  
V7  
V4  
V8  
OUT  
OUT  
Figure 46. AD7606 Serial Interface with Two DOUT Lines  
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