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AD7606BSTZ 参数 Datasheet PDF下载

AD7606BSTZ图片预览
型号: AD7606BSTZ
PDF下载: 下载PDF文件 查看货源
内容描述: 8 / 6 / 4通道DAS,内置16位,双极性输入,同步采样ADC [8-/6-/4-Channel DAS with 16-Bit,Bipolar Input,Simultaneous Sampling ADC]
分类和应用: 转换器模数转换器PC
文件页数/大小: 36 页 / 781 K
品牌: ADI [ ADI ]
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AD7606/AD7606-6/AD7606-4  
transformers. In a 50 Hz system, this allows for up to 9° of phase  
compensation; and in a 60 Hz system, it allows for up to 10° of  
phase compensation.  
CONVERSION CONTROꢀ  
Simultaneous Sampling on All Analog Input Channels  
The AD7606/AD7606-6/AD7606-4 allow simultaneous sampling  
of all analog input channels. All channels are sampled simul-  
taneously when both CONVST pins (CONVST A, CONVST B)  
are tied together. A single CONVST signal is used to control both  
CONVST x inputs. The rising edge of this common CONVST  
signal initiates simultaneous sampling on all analog input channels  
(V1 to V8 for the AD7606, V1 to V6 for the AD7606-6, and V1  
to V4 for the AD7606-4).  
This is accomplished by pulsing the two CONVST pins  
independently and is possible only if oversampling is not in use.  
CONVST A is used to initiate simultaneous sampling of the  
first set of channels (V1 to V4 for the AD7606, V1 to V3 for the  
AD7606-6, and V1 and V2 for the AD7606-4); and CONVST B  
is used to initiate simultaneous sampling on the second set of  
analog input channels (V5 to V8 for the AD7606, V4 to V6 for  
the AD7606-6, and V3 and V4 for the AD7606-4), as illustrated  
in Figure 44. On the rising edge of CONVST A, the track-and-  
hold amplifiers for the first set of channels are placed into hold  
mode. On the rising edge of CONVST B, the track-and-hold  
amplifiers for the second set of channels are placed into hold  
mode. The conversion process begins once both rising edges  
of CONVST x have occurred; therefore BUSY goes high on the  
rising edge of the later CONVST x signal. In Table 3, Time t5  
indicates the maximum allowable time between CONVST x  
sampling points.  
The AD7606 contains an on-chip oscillator that is used to  
perform the conversions. The conversion time for all ADC  
channels is tCONV. The BUSY signal indicates to the user when  
conversions are in progress, so when the rising edge of CONVST  
is applied, BUSY goes logic high and transitions low at the end  
of the entire conversion process. The falling edge of the BUSY  
signal is used to place all eight track-and-hold amplifiers back  
into track mode. The falling edge of BUSY also indicates that  
the new data can now be read from the parallel bus (DB[15:0]),  
the DOUTA and DOUTB serial data lines, or the parallel byte bus,  
DB[7:0].  
There is no change to the data read process when using two  
separate CONVST x signals.  
Simultaneously Sampling Two Sets of Channels  
Connect all unused analog input channels to AGND. The results  
for any unused channels are still included in the data read because  
all channels are always converted.  
The AD7606/AD7606-6/AD7606-4 also allow the analog input  
channels to be sampled simultaneously in two sets. This can be  
used in power-line protection and measurement systems to  
compensate for phase differences introduced by PT and CT  
V1 TO V4 TRACK-AND-HOLD  
ENTER HOLD  
V5 TO V8 TRACK-AND-HOLD  
ENTER HOLD  
t5  
CONVST A  
CONVST B  
BUSY  
AD7606 CONVERTS  
ON ALL 8 CHANNELS  
tCONV  
CS/RD  
V1  
V2  
V3  
V7  
V8  
DATA: DB[15:0]  
FRSTDATA  
Figure 44. AD7606 Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B Signals—Parallel Mode  
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