AD7569/AD7669–TIMING CHARACTERISTICS1
(See Figures 8, 10, 12; VDD = 5 V ؎ 5%; VSS = 0 V or –5 V ؎ 5%)
Limit at
Limit at
Limit at
25؇C (All Grades)
TMIN, TMAX
(J, K, A, B Grades)
TMIN, TMAX
(S, T Grades)
Parameter
Units
Test Conditions/Comments
DAC Timing
t1
t2
t3
t4
t5
80
0
0
60
10
80
0
0
70
10
90
0
0
80
10
ns min
ns min
ns min
ns min
ns min
WR Pulse Width
CS, A/B to WR Setup Time
CS, A/B to WR Hold Time
Data Valid to WR Setup Time
Data Valid to WR Hold Time
ADC Timing
t6
t7
t8
t9
50
110
20
0
0
60
0
60
95
10
60
65
120
60
90
50
130
30
0
0
75
0
75
120
10
75
75
140
75
115
50
150
30
0
0
90
0
90
135
10
85
85
160
90
135
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns max
ns max
ns max
ST Pulse Width
ST to BUSY Delay
BUSY to INT Delay
BUSY to CS Delay
CS to RD Setup Time
RD Pulse Width Determined by t13.
CS to RD Hold Time
Data Access Time after RD; CL = 20 pF
Data Access Time after RD; CL = 100 pF
Bus Relinquish Time after RD
t10
t11
t12
2
t13
3
t14
t15
t16
t17
RD to INT Delay
RD to BUSY Delay
Data Valid Time after BUSY; CL = 20 pF
Data Valid Time after BUSY; CL = 100 pF
2
NOTES
1Sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2t13 and t17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either 0.8 V or 2.4 V.
3tl4 is defined as the time required for the data line to change 0.5 V when loaded with the circuit of Figure 2.
Specifications subject to change without notice.
a. High-Z to VOH
b. High-Z to VOL
a. VOH to High-Z
b. VOL to High-Z
Figure 1. Load Circuits for Data Access Time Test
Figure 2. Load Circuits for Bus Relinquish Time Test
ABSOLUTE MAXIMUM RATINGS
VDD to AGNDDAC or AGNDADC . . . . . . . . . . . . . –0.3 V, +7 V
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial (J, K) . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial (A, B) . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S, T) . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other condition above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
V
V
DD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
DD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +14 V
AGNDDAC or AGNDADC to DGND . . . . –0.3 V, VDD + 0.3 V
AGNDDAC to AGNDADC . . . . . . . . . . . . . . . . . . . . . . . . . ±5 V
Logic Voltage to DGND . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
CLK Input Voltage to DGND . . . . . . . . . –0.3 V, VDD + 0.3 V
V
OUT (VOUTA, VOUTB) to
AGND1
. . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
DAC
V
IN to AGNDADC . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
NOTE
1Output may be shorted to any voltage in the range VSS to VDD provided that the
power dissipation of the package is not exceeded. Typical short circuit current for
a short to AGND or VSS is 50 mA.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7569/AD7669 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
ADI [ ADI ]
