AD7569/AD7669
(VDD = +5 V ؎ 5%; VSS1 = RANGE = AGNDDAC = AGNDDAC = DGND = 0 V; fCLK = 5 MHz external unless other-
wise noted. All specifications TMIN to TMAX unless otherwise noted.) Specifications apply to Mode 1 interface.
ADC SPECIFICATIONS
AD7569
J, A Versions3 AD7569
AD7669
K, B
AD7569
AD7569
Parameter
J Version
Versions
S Version
T Version
Units
Conditions/Comments
DC ACCURACY
Resolution3
8
8
8
8
Bits
Total Unadjusted Error4
Relative Accuracy4
Differential Nonlinearity4
Unipolar Offset Error
@ +25°C
±3
±1
±1
±3
±1/2
±3/4
±4
±1
±1
±4
±1/2
±3/4
LSB typ
LSB max
LSB max
No Missing Codes
Typical tempco is 10 µV/°C for +1.25 V range; VSS = 0 V
±2
±3
±1.5
±2.5
±2
±3
±1.5
±2.5
LSB max
LSB max
T
MIN to TMAX
Bipolar Zero Offset Error
@ +25°C
TMIN to TMAX
Full-Scale Error5
@ +25°C
Typical tempco is 20 µV/°C for + 1.25 V range; VSS = –5 V
±3
±3.5
±2.5
±3
±3
±4
±2.5
±3.5
LSB max
LSB max
VDD = 5 V
–4, +0
–5.5, +1.5
0.5
–4, +0
–5.5, +1.5
0.5
–4, +0
–7.5, +2
0.5
–4, +0
–7.5, +2
0.5
LSB max
LSB max
LSB max
LSB max
T
MIN to TMAX
∆Full Scale/∆VDD, TA = +25°C
∆Full Scale/∆VSS, TA = +25°C
VIN = +2.5 V; ∆VDD = ±5%
VIN = –2.5 V; ∆VSS = ±5%
0.5
0.5
0.5
0.5
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio4 (SNR)
Total Harmonic Distortion4 (THD)
Intermodulation Distortion4 (IMD)
Frequency Response
44
48
60
0.1
200
46
48
60
0.1
200
44
48
60
0.1
300
45
48
60
0.1
300
dB min
dB max
dB typ
dB typ
ns typ
VIN = 100 kHz full-scale sine wave with fSAMPLING = 400 kHz6
VIN = 100 kHz full-scale sine wave with fSAMPLING = 400 kHz6
fa = 99 kHz, fb = 96.7 kHz with fSAMPLING = 400 kHz
V
IN = ±2.5 V, dc to 200 kHz sine wave
Track/Hold Acquisition Time7
ANALOG INPUT
Input Voltage Ranges
Unipolar
Bipolar
Input Current
Input Capacitance
0 to +1.25/ +2.5
±1.25/±2.5
±300
Volts
Volts
µA max
pF typ
V
V
DD = +5 V; VSS = 0 V
DD = +5 V; VSS = –5 V
±300
10
±300
10
±300
10
See equivalent circuit Figure 5
10
LOGIC INPUTS
CS, RD, ST, CLK, RESET, RANGE
Input Low Voltage, VINL
Input High Voltage, VINH
Input Capacitance8
CS, RD, ST, RANGE, RESET
Input Leakage Current
CLK
0.8
2.4
10
0.8
2.4
10
0.8
2.4
10
0.8
2.4
10
V max
V min
pF max
10
10
10
10
µA max
V IN = 0 to VDD
Input Current
IINL
IINH
–1.6
40
–1.6
40
–1.6
40
–1.6
40
mA max
µA max
VIN = 0 V
VIN = VDD
LOGIC OUTPUTS
DB0–DB7, INT, BUSY
VOL, Output Low Voltage
0.4
4.0
0.4
4.0
0.4
4.0
0.4
4.0
V max
V min
ISINK = 1.6 mA
ISOURCE = 200 µA
V
OH, Output High Voltage
DB0–DB7
Floating State Leakage Current
Floating State Output Capacitance8
Output Coding (Single Supply)
Output Coding (Dual Supply)
10
10
10
10
Binary
10
10
10
10
µA max
pF max
2s Complement
CONVERSION TIME
With External Clock
With Internal Clock, TA = +25°C
2
1.6
2.6
2
1.6
2.6
2
1.6
2.6
2
1.6
2.6
µs max
µs min
µs max
f
CLK = 5 MHz
Using recommended clock components shown in Figure 21.
Clock frequency can be adjusted by varying RCLK
.
POWER REQUIREMENTS
As per DAC Specifications
NOTES
1
Except where noted, specifications apply for all ranges including bipolar ranges with dual supply operation.
2Temperature ranges are as follows: J, K versions; 0°C to +70°C
A, B versions; –40°C to +85°C
S, T versions; –55°C to +125°C
31 LSB = 4.88 mV for 0 V to +1.25 V range, 9.76 mV for 0 V to +2.5 V and ±1.25 V ranges and 19.5 mV for +2.5 V range.
4See Terminology.
5Includes internal voltage reference error and is calculated after offset error has been adjusted out. Ideal unipolar last code transition occurs at (FS – 3/2 LSB). Ideal bipolar last code transition occurs at
(FS/2 – 3/2 LSB).
6Exact frequencies are 101 kHz and 384 kHz to avoid harmonics coinciding with sampling frequency.
7Rising edge of BUSY to falling edge of ST. The time given refers to the acquisition time, which gives a 3 dB degradation in SNR from the tested figure.
8Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
REV. B
–3–
ADI [ ADI ]
