AD7545
CIRCUIT INFORMATION—D/A CONVERTER SECTION
Figure 1 shows a simplified circuit of the D/A converter section
of the AD7545 and Figure 2 gives an approximate equivalent
circuit. Note that the ladder termination resistor is connected to
AGND. R is typically 11 kΩ.
V
REF
R
R
R
R
power supply. To minimize power supply currents it is recom-
mended that the digital input voltages be as close as practicably
possible to the supply rails (V
DD
and DGND).
The AD7545 may be operated with any supply voltage in the
range 5
≤
V
DD
≤
15 volts. With V
DD
= +15 V the input logic
levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.
BASIC APPLICATIONS
2R
2R
2R
2R
2R
2R
R
FB
OUT 1
AGND
DB11
(MSB)
DB10
DB9
DB1
DB0
(LSB)
Figure 1. Simplified D/A Circuit of AD7545
Figures 4 and 5 show simple unipolar and bipolar circuits using
the AD7545. Resistor R1 is used to trim for full scale. The
“G” versions (AD7545GLN, AD7545GCQ, AD7545GUD)
have a guaranteed maximum gain error of
±
1 LSB at +25°C
(V
DD
= +5 V), and in many applications it should be possible to
dispense with gain trim resistors altogether. Capacitor C1 provides
phase compensation and helps prevent overshoot and ringing when
using high speed op amps. Note that all the circuits of Figures 4, 5
and 6 have constant input impedance at the V
REF
terminal.
The circuit of Figure 1 can either be used as a fixed reference
D/A converter so that it provides an analog output voltage in the
range 0 to –V
IN
(note the inversion introduced by the op amp),
or V
IN
can be an ac signal in which case the circuit behaves as
an attenuator (2-Quadrant Multiplier). V
IN
can be any voltage
in the range –20
≤
V
IN
+ 20 volts (provided the op amp can
handle such voltages) since V
REF
is permitted to exceed V
DD
.
Table II shows the code relationship for the circuit of Figure 4.
V
DD
R2
*
20
R
FB
OUT1 1
AGND
DGND
3
ANALOG
COMMON
DB11–DB0
2
AD544L
(SEE TEXT)
C1
33pF
V
OUT
The binary weighted currents are switched between the OUT1
bus line and AGND by N-channel switches, thus maintaining a
constant current in each ladder leg independent of the switch
state.
The capacitance at the OUT1 bus line, C
OUT1
, is code depen-
dent and varies from 70 pF (all switches to AGND) to 200 pF
(all switches to OUT1).
One of the current switches is shown in Figure 2. The input
resistance at V
REF
(Figure 1) is always equal to R
LDR
(R
LDR
is
the R/2R ladder characteristic resistance and is equal to value
“R”). Since R
IN
at the V
REF
pin is constant, the reference termi-
nal can be driven by a reference voltage or a reference current,
ac or dc, of positive or negative polarity. (If a current source is
used, a low temperature coefficient external R
FB
is recommended
to define scale factor.)
TO LADDER
18
V
IN
R1
*
V
DD
19 V
REF
AD7545
FROM
INTERFACE
LOGIC
*
REFER TO TABLE I
Figure 4. Unipolar Binary Operation
Table I. Recommended Trim Resistor Values vs. Grades for
V
DD
= +5 V
AGND
OUT 1
Figure 2. N-Channel Current Steering Switch
CIRCUIT INFORMATION—DIGITAL SECTION
Trim
Resistor
R1
R2
J/A/S
500
Ω
150
Ω
K/B/T
200
Ω
68
Ω
L/C/U
100
Ω
33
Ω
GL/GC/GU
20
Ω
6.8
Ω
Figure 3 shows the digital structure for one bit.
The digital signals CONTROL and
CONTROL
are generated
from
CS
and
WR.
TO AGND SWITCH
V
IN
TO OUT1 SWITCH
Table II. Unipolar Binary Code Table for Circuit of Figure 4
Binary Number in DAC Register Analog Output
4095
–V
IN
4096
2048
–V
IN
4096
= –1/2 V
IN
1
–V
IN
4096
0 Volts
INPUT BUFFERS
1111
CONTROL
CONTROL
1111
1111
Figure 3. Digital Input Structure
1000
0000
0000
The input buffers are simple CMOS inverters designed so that
when the AD7545 is operated with V
DD
= 5 V, the buffers con-
vert TTL input levels (2.4 V and 0.8 V) into CMOS logic levels.
When V
IN
is in the region of 2.0 volts to 3.5 volts, the input
buffers operate in their linear region and draw current from the
–4–
0000
0000
0000
0000
0001
0000
REV. A
AD [ ANALOG DEVICES ]
