AD7545
t
CS
CHIP
SELECT
t
CH
V
DD
0
WRITE MODE:
MODE SELECTION
HOLD MODE:
EITHER
CS
OR
WR
HIGH, DATA BUS
(DB0–DB11) IS LOCKED OUT; DAC
HOLDS LAST DATA PRESENT WHEN
WR
OR
CS
ASSUMED HIGH STATE.
CS
AND
WR
LOW, DAC RESPONDS
TO DATA BUS (DB0–DB11) INPUTS.
t
WR
WRITE
V
DD
0
t
DS
DATA IN
(DB0–DB11)
V
IH
V
IL
DATA VALID
t
DH
V
DD
0
NOTES:
V
DD
= +5V; t
r
= t
f
= 20ns
V
DD
= +15V; t
r
= t
f
= 40ns
ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO
90% OF V
DD
.
TIMING MEASUREMENT REFERENCE LEVEL IS V
IH
+ V
IL
/2.
Write Cycle Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
(T
A
= + 25°C unless otherwise noted)
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +17 V
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
DD
+0.3 V
V
RFB
, V
REF
to DGND . . . . . . . . . . . . . . . . . . . . . . . . .
±
25 V
V
PIN1
to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
Commercial (J, K, L, GL) Grades . . . . . . . . 0°C to +70°C
Industrial (A, B, C, GC) Grades . . . . . . . . –25°C to +85°C
Extended (S, T, U, GU) Grades . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7545 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
RELATIVE ACCURACY
ORDERING GUIDE
1
Maximum
Gain Error
T
A
= +25 C
V
DD
= +5 V
±
20 LSB
±
20 LSB
±
20 LSB
±
10 LSB
±
10 LSB
±
10 LSB
±
5 LSB
±
5 LSB
±
5 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
20 LSB
±
20 LSB
±
10 LSB
±
10 LSB
±
5 LSB
±
5 LSB
±
1 LSB
±
1 LSB
The amount by which the D/A converter transfer function
differs from the ideal transfer function after the zero and full-
scale points have been adjusted. This is an endpoint linearity
measurement.
DIFFERENTIAL NONLINEARITY
Model
2
AD7545JN
AD7545AQ
AD7545SQ
AD7545KN
AD7545BQ
AD7545TQ
AD7545LN
AD7545CQ
AD7545UQ
AD7545GLN
AD7545GCQ
AD7545GUQ
AD7545JP
AD7545SE
AD7545KP
AD7545TE
AD7545LP
AD7545UE
AD7545GLP
AD7545GUE
Temperature
Range
0°C to +70°C
–25°C to +85°C
–55°C to +125°C
0°C to +70°C
–25°C to +85°C
–55°C to +125°C
0°C to +70°C
–25°C to +85°C
–55°C to +125°C
0°C to +70°C
–25°C to +85°C
–55°C to +125°C
0°C to +70°C
–55°C to +125°C
0°C to +70°C
–55°C to +125°C
0°C to +70°C
–55°C to +125°C
0°C to +70°C
–55°C to +125°C
Relative
Accuracy
±
2 LSB
±
2 LSB
±
2 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1/2 LSB
±
1/2 LSB
±
1/2 LSB
±
1/2 LSB
±
2 LSB
±
2 LSB
±
1 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1/2 LSB
±
1/2 LSB
Package
Options
3
N-20
Q-20
Q-20
N-20
Q-20
Q-20
N-20
Q-20
Q-20
N-20
Q-20
Q-20
P-20A
E-20A
P-20A
E-20A
P-20A
E-20A
P-20A
E-20A
The difference between the measured change and the ideal
change between any two adjacent codes. If a device has a differ-
ential nonlinearity of less than 1 LSB it will be monotonic, i.e.,
the output will always increase for an increase in digital code
applied to the D/A converter.
PROPAGATION DELAY
This is a measure of the internal delay of the circuit and is mea-
sured from the time a digital input changes to the point at which
the analog output at OUT1 reaches 90% of its final value.
DIGITAL-TO-ANALOG GLITCH IMPULSE
This is a measure of the amount of charge injected from the
digital inputs to the analog outputs when the inputs change
state. It is usually specified as the area of the glitch in nV secs
and is measured with V
REF
= AGND and an ADLH0032CG as
the output op amp, C1 (phase compensation) = 33 pF.
NOTES
1
Analog Devices reserves the right to ship either ceramic (D-20) in lieu of cerdip
packages (Q-20).
2
To order MIL-STD-883, Class B process parts, add /883B to part number.
Contact local sales office for military data sheet. For U.S. Standard Military
DRAWING (SMD) see DESC drawing 5962-87702.
3
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip.
REV. A
–3–
AD [ ANALOG DEVICES ]
