AD7228A
+5 V SUPPLY OPERATION
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Zero Code Error
@ 25°C
T
MIN
to T
MAX
REFERENCE INPUT
Reference Input Range
Reference Input Resistance
Reference Input Capacitance
POWER REQUIREMENTS
Positive Supply Range
Positive Supply Current
@ 25°C
T
MIN
to T
MAX
Negative Supply Current
@ 25°C
T
MIN
to T
MAX
8
±
2
±
1
±
4
±
30
±
40
1.2
1.3
2
500
4.75/5.25
16
20
14
18
(V
DD
= +5 V 5%, V
SS
; = 0 to –5 V 10%, GND = 0 V, V
REF
= +1.25 V, R
L
= 2 k , C
L
= 100 pF
unless otherwise noted.) AII specifications T
MIN
to T
MAX
unless otherwise noted.
C
Version
8
±
2
±
1
±
2
±
20
±
30
1.2
1.3
2
500
4.75/5.25
16
20
14
18
T
Version
8
±
2
±
1
±
4
±
30
±
40
1.2
1.3
2
500
4.75/5.25
16
22
14
20
U
Version
8
±
2
±
1
±
2
±
20
±
30
1.2
1.3
2
500
4.75/5.25
16
22
14
20
Units
Bits
LSB max
LSB max
LSB max
mV max
mV max
V min
V max
kΩ min
pF max
V min/V max
µA
max
µA
max
µA
max
µA
max
For Specified Performance
Conditions/Comments
B
Version
Guaranteed Monotonic
NOTES
All of the specifications as per Dual Supply Specifications except for negative full-scale settling-time when V
SS
= 0 V.
Specifications subject to change without notice.
SWITCHING CHARACTERISTICS
1, 2
Parameters
t
1
t
2
t
3
t
4
t
5
Limit at 25°C
All Grades
0
0
70
10
95
(See Figures 1, 2; V
DD
= +5 V
5% or +10.8 V to +16.5 V; V
SS
= 0 V or –5 V
Units
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
10%)
Limit at T
MIN
, T
MAX
(B, C Versions)
0
0
90
10
120
Limit at T
MIN
, T
MAX
(T, U Versions)
0
0
100
10
150
Address to
WR
Setup Time
Address to
WR
Hold Time
Data Valid to
WR
Setup Time
Data Valid to
WR
Hold Time
Write Pulse Width
NOTES
1
Sample tested at 25°C to ensure compliance. All input rise and fall times measured from 10% to 90% of +5 V, t
R
= t
F
= 5 ns.
2
Timing measurement reference level is
V
INH
+
V
INL
2
INTERFACE LOGIC INFORMATION
Address lines A0, A1 and A2 select which DAC accepts data
from the input port. Table I shows the selection table for the
eight DACs with Figure 1 showing the input control logic.
When the
WR
signal is low, the input latch of the selected DAC
is transparent, and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of
WR.
While
WR
is high, the analog outputs remain
at the value corresponding to the data held in their respective
latches.
Table I. AD7228A Truth Table
AD7228A Control Inputs
WR
A2
A1
H
L
X
L
L
L
L
L
H
H
H
H
X
L
L
L
H
H
L
L
H
H
A0
X
L
L
H
L
H
L
H
L
H
AD7228A
Operation
No Operation
Device Not Selected
DAC 1 Transparent
DAC 1 Latched
DAC 2 Transparent
DAC 3 Transparent
DAC 4 Transparent
DAC 5 Transparent
DAC 6 Transparent
DAC 7 Transparent
DAC 8 Transparent
Figure 1. Input Control Logic
g
L
L
L
L
L
L
L
H = High State L = Low State X = Don’t Care
Figure 2. Write Cycle Timing Diagram
REV. A
–3–
AD [ ANALOG DEVICES ]
