AD7011
ANALOG MODE TIMING
Parameter
t
20
t
21
t
22
t
23
t
24
15
15
15t
1
16t
1
15
15
(V
AA
= V
DD
= +5 V
otherwise noted.)
10%. AGND = DGND = 0 V. All specifications are T
MIN
to T
MAX
unless
Units
ns min
ns min
ns max
ns
ns min
ns min
Description
MCLK Rising Edge to FRAME Setup Time.
MCLK Rising Edge to FRAME Hold Time.
FRAME Cycle Time.
MCLK Rising Edge to Data Setup Time.
MCLK Rising Edge to Data Hold Time.
Limit at T
A
= –40°C to +85°C
MCLK
t
20
FRAME
t
22
t
21
t
23
t
24
I DATA
DB9
DB8
DB1
DB0
DB9
DB8
DB7
Q DATA
DB9
DB8
DB1
DB0
DB9
DB8
DB7
Figure 6. Analog Mode Serial Interface Timing
Q
MODULAR OUTPUT
DURING FTEST
I
Table I.
MODE 1
0
1
0
1
MODE 2
0
0
1
1
Operation
Digital TIA Mode
Analog Mode
FTEST
Factory Test, Reserved
Figure 7. Modulator State During FTEST
Table II.
Mode of Operation
Digital Mode
Analog Mode
MODE 1
0
1
MODE 2
0
0
MCLK
3.1104 MHz
2.56 MHz
Digital Bit Rate
48.6 kHz
N/A
DAC Update Rate
N/A
160 kHz
REV. B
–5–
AD [ ANALOG DEVICES ]
