AD7011
TRANSMIT SECTION TIMING
Parameter
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
10
t
1
– 10
4097t
1
+ 70
10
t
1
– 10
t
1
+ 70
3t
1
+ 70
64t
1
32t
1
32t
1
50
0
3t
1
124t
1
7.5t
9
30t
1
10
10
(V
AA
= V
DD
= +5 V 10%; AGND = DGND = 0 V, f
MCLK
= 3.1104 MHz. All specifications are
T
MIN
to T
MAX
unless otherwise noted.)
Units
ns min
ns max
ns max
ns min
ns max
ns max
ns
ns
ns
ns
ns min
ns min
ns max
ns max
ns
ns max
ns max
ns max
Description
Power Setup Time.
MCLK rising edge, after Power high, to READY rising edge.
BIN Setup Time.
MCLK to READY propagation delay.
MCLK rising edge, after BIN high, to first TxCLK rising edge.
TxCLK Cycle Time.
TxCLK High Time.
TxCLK Low Time.
TxCLK falling edge to TxDATA setup time.
TxCLK falling edge to TxDATA hold time.
BIN low setup to Last transmitted symbol after ramp down.
BIN low hold to Last transmitted symbol after ramp down.
Ramp Down cycle time after the last transmitted symbol.
Last TxCLK falling edge to READY rising edge.
Digital Output Rise Time.
Digital Output Fall Time.
Limit at T
A
= –40 C to +85 C
MCLK
POWER
t
4
READY
t
7
t
5
BIN
t
6
t
8
t
9
t
11
t
12
t
13
t
10
X
Y
TxCLK
TxDATA
k
k
Figure 4. Transmit Timing at the Start of a Tx Burst
MCLK
POWER
t
17
READY
BIN
t
14
t
15
TxCLK
t
16
TxDATA
X
N+4
Y
N+4
X
N+5
X
N+8
Y
N+8
Figure 5. Transmit Timing at the End of a Tx Burst
–4–
REV. B
AD [ ANALOG DEVICES ]
