AD6620
TIMING DIAGRAMS
CLK, INPUTS, PARALLEL OUTPUTS
SYNC PULSES: SLAVE OR MASTER
RESET with PAR/SER = “1” establishes Parallel Outputs active.
t
CLK
t
CLKH
CLK
t
SY
SYNC NCO
SYNC CIC
SYNC RCF
t
HY
CLK
t
CLKL
Figure 6. SYNC Slave Timing Requirements
Figure 3. CLK Timing Requirements
t
DY
CLK
CLK
t
SI
IN[15:0]
EXP[2:0]
A/B
DATA
t
HI
SYNC NCO
SYNC CIC
SYNC RCF
Figure 7. SYNC Master Delay
Figure 4. Input Data Timing Requirements
t
DPR
t
DPF
t
DPF
RESET
CLK
t
RESL
DV
OUT
VALID OUTPUT DATA
Figure 8. Reset Timing Requirements
I/Q
OUT
I
Q
I
Q
OUT[15:0]
I
A
Q
A
I
B
Q
B
Figure 5. Parallel Output Switching Characteristics
REV. 0
–7–