AD6620
MICROPORT MODE1, READ
Timing is synchronous to CLK; MODE = 1.
tDD
tHC
1
N
N+3
N+4
N+1
N+2
N
CLK
2
tSC
R/W
2
DS
tSC
tHC
3
CS
tZD
tZR
DATA VALID
D[7:0]
A[2:0]
tSAM
tHA
ADDRESS VALID
tDTACK
tDTACK
DTACK
NOTES:
1
DTACK IS DRIVEN LOW ON THE RISING EDGE OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000),
CLK "N=2" OTHERWISE.
2
THE SIGNAL, R/W MAY REMAIN HIGH AND DS MAY REMAIN LOW TO CONTINUE READ MODE.
3
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE ACCESS
AND FORCE DTACK HIGH.
Figure 19. MODE1 Read Timing Requirements and Switching Characteristics
MICROPORT MODE1, WRITE
Timing is synchronous to CLK; MODE = 1.
tSC
tHC
N+2
1
CLK
N
N+3
N*
N+1
2
R/W
2
DS
tHC
tSC
3
CS
tSAM
tHM
D[7:0]
DATA VALID
tSAM
tHA
A[2:0]
ADDRESS VALID
tDTACK
DTACK
tDTACK
NOTES:
1
ON RISING EDGE OF "N+3" CLK, DTACK IS DRIVEN LOW.
2
3
THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE
AND FORCE DTACK HIGH.
* THE NEXT WRITE MAY BE INITIATED ON CLK, N*.
Figure 20. MODE1 Write Timing Requirements and Switching Characteristics
–10–
REV. 0
ADI [ ADI ]
