AD6620
The set of plots below (Figure 39) represents a decimation of 32
in the CIC5 filter. It can be seen that the lobes of the filter drop
as the decimation rate increases, but the aliased frequencies
increase due to the reduction of the output rate.
The maximum number of taps this filter can calculate, NTAPS, is
given by the equation below. The value NTAPS minus 1 is writ-
ten to the AD6620 internal address space at address 30C hex.
The decimation ratio of this filter, MRCF, may be programmed
from 1 to 32. The input rate into the RCF is fSAMP5. NCH is equal
to two for Diversity Channel Real Input mode; otherwise NCH = 1.
0
–20
–40
fCLK × MRCF
min
, 256
fSAMP5
NTAPS
≤
NCH
–60
–80
The RCF coefficients are located in addresses 0x000 to 0x0FF
and are interpreted as 20-bit twos complement numbers. When
writing the coefficient RAM, the lower addresses will be multi-
plied by relatively older data from the CIC5 and the higher
coefficient addresses will be multiplied by relatively newer data
from the CIC5. The coefficients need not be symmetric and the
coefficient length, NTAPS, may be even or odd. If the coefficients
are symmetric, then both sides of the impulse response must be
written into the coefficient RAM.
–100
–120
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
f/f
SAMP
0
The RCF stores the data from the CIC5 into a 256 × 36 RAM.
256 × 18 is assigned to I data and 256 × 18 is assigned to Q data.
The RCF uses the RAM as a circular buffer, so that it is difficult
to know in which address a particular data element is stored. To
avoid start-up transients due to undefined data RAM values, the
data RAM should be cleared upon initialization. The RCF
–20
–40
–60
–80
utilizes the number of data RAM locations equal to NTAPS × NCH
,
rounded up to the nearest even number, starting from address
0x100, so these are the only values that need be cleared.
When the RCF is triggered to calculate a filter output, it starts
by multiplying the oldest value in the data RAM by the first
coefficient (located by the RCFOFF register in address 0x30B).
This value is accumulated with the products of newer data words
multiplied by the subsequent locations in the coefficient RAM
until the coefficient address RCFOFF + NTAPS–1 is reached.
–100
–120
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1 0.2
0.3
0.4
0.5
f/f
SAMP5
Figure 39. CIC5 Alias Rejection, MCIC5 = 32
Table V. Three-Tap Filter
RAM COEFFICIENT FILTER
Coefficient Address
Impulse Response
Data
The final signal processing stage is a sum-of-products decimat-
ing filter with programmable coefficients. Figure 40 shows a
simplified block diagram. The data memories I-RAM and Q-RAM
store the 256 most recent complex samples from the previous filter
stage with 18-bit resolution. The coefficient memory, C-RAM,
stores up to 256 coefficients with 20-bit resolution. On each
CLK cycle one tap for I and one tap for Q is calculated using
the same coefficients. The I and Q accumulators provide 3 bits
of headroom. This headroom allows the output of the RCF filter
to contain 23 significant bits.
0
1
h(0)
h(1)
h(2)
n(0) Newest
n(1)
n(2) Oldest
2 (NTAPS – 1)
The output rate of this filter is determined by the output rate of
the CIC5 stage and MRCF.
fSAMP5
MRCF
fSAMPR
=
RCF Coefficient Address Offset
I
I
IN
OUT
This register at address 30b hex allows the AD6620 to hold
multiple filters in the RAM. However, the sum of the taps
required may not exceed 256 divided by the number of chan-
nels. The RCF will compute the filter from RCF_OFFSET to
(RCF_OFFSET + NTAPS). A single access can then be used to
select which of the filters is used without requiring coefficients
be rewritten.
I-RAM
C-RAM
Q-RAM
Q
Q
OUT
IN
Figure 40. RAM Coefficient Filter Block Diagram
REV. A
–25–
ADI [ ADI ]
