AD654
5V
GND
FREQUENCY DOUBLING
20pF
6MHz
1 F
V
CC
XTAL1
V
DD
V
SS
P10
PORT 1
P17
20pF
XTAL2
RESET
EA
NC
SS
INT
T0
T1
ALE
PSEN
PROG
WR
NC
5V
NC
P20
PORT 2
P27
DB0
DB7
RD
BUS
PORT
Since the AD654’s output is a square-wave rather than a pulse
train, information about the input signal is carried on both
halves of the output waveform. The circuit in Figure 12 converts
the output into a pulse train, effectively doubling the output
frequency, while preserving the better low frequency linearity of
the AD654. This circuit also accommodates an input voltage
that is greater than the AD654 supply voltage.
Resistors R1–R3 are used to scale the 0 V to +10 V input voltage
down to 0 V to +1 V as seen at Pin 4 of the AD654. Recall that
V
IN
must be less than V
SUPPLY
–4 V, or in this case less than 1 V.
The timing resistor and capacitor are selected such that this 0 V
to +1 V signal seen at Pin 4 results in a 0 kHz to 200 kHz output
frequency.
The use of R4, C1 and the XOR gate doubles this 200 kHz
output frequency to 400 kHz. The AD654 output transistor is
basically used as a switch, switching capacitor C1 between a
charging mode and a discharging mode of operation. The voltages
seen at the input of the 74LS86 are shown in the waveform dia-
gram. Due to the difference in the charge and discharge time
constants, the output pulse widths of the 74LS86 are not equal.
The output pulse is wider when the capacitor is charging due to
its longer rise time than fall time. The pulses should therefore be
counted on their rising, rather than falling, edges.
8048
NC = NO CONNECT
10k
1
2
3
8
AD654
7
1000pF
6
5
+
1k
4
V
IN
(0V TO 1V)
–
D
825
1%
500
A
Figure 11. AD654 VFC as an ADC
5V
R
PU
2.87k
R1
8.06k
R2
2k
AD654
OSC/
DRIVER
C1
1000pF
R4
1k
A
B
74LS86
C
V
IN
(0V TO 10V)
R3
1k
R
T
1k
C
T
500pF
OFF
ON
V
0
V
0
5
0
WAVEFORM DIAGRAM
V/F OUTPUT
FS = 400MHz
TRANSISTOR
A
B
C
Figure 12. Frequency Doubler
REV. B
–9–
AD [ ANALOG DEVICES ]
