AD654
CIRCUIT OPERATION
The AD654’s block diagram appears in Figure 1. A versatile
operational amplifier serves as the input stage; its purpose is to
convert and scale the input voltage signal to a drive current in the
NPN follower. Optimum performance is achieved when, at the
full-scale input voltage, a 1 mA drive current is delivered to the
current-to-frequency converter (an astable multivibrator). The
drive current provides both the bias levels and the charging current
to the externally connected timing capacitor. This “adaptive” bias
scheme allows the oscillator to provide low nonlinearity over
the entire current input range of 100 nA to 2 mA. The square
wave oscillator output goes to the output driver which provides
a floating base drive to the NPN power transistor. This floating
drive allows the logic interface to be referenced to a level other
than –V
S
.
+V
S
(+5V TO –V
S
+30)
C
T
+V
LOGIC
R
PU
OPTIONAL
R
COMP
F
OUT
OSC/
DRIVER
F
OUT
=
V
IN
(10V) (R1 + R2) C
T
V/F CONNECTIONS FOR NEGATIVE INPUT VOLTAGE
OR CURRENT
The AD654 can accommodate a wide range of negative input
voltages with proper selection of the scaling resistor, as indicated
in Figure 2. This connection, unlike the buffered positive con-
nection, is not high impedance because the signal source must
supply the 1 mA FS drive current. However, large negative volt-
ages beyond the supply can be handled easily by modifying the
scaling resistors appropriately. If the input is a true current source,
R1 and R2 are not used. Again, diode CR1 prevents latch-up by
insuring Logic Common does not drop more than 500 mV below
–V
S
. The clamp diode (MBD101) protects the AD654 input
from “below –V
S
” inputs.
+V
S
(+5V TO –V
S
+30)
C
T
+V
LOGIC
R
PU
OPTIONAL
R
COMP
F
OUT
OSC/
DRIVER
F
OUT
=
V
IN
R1
R2
V
IN
(10V) (R1 + R2) C
T
V
IN
AD654
AD654
R1
R2
CR1
–V
S
(0V TO –15V)
CLAMP
DIODE
CR1
–V
S
(0V TO –15V)
Figure 2. V-F Connections for Negative Input Voltages or
Current
OFFSET CALIBRATION
Figure 1. Standard V-F Connection for Positive Input
Voltages
V/F CONNECTION FOR POSITIVE INPUT VOLTAGES
In the connection scheme of Figure 1, the input amplifier presents
a very high (250 MΩ) impedance to the input voltage, which
is converted into the proper drive current by the scaling resistors
at Pin 3. Resistors R1 and R2 are selected to provide a 1 mA
full-scale current with enough trim range to accommodate the
AD654’s 10% FS error and the components’ tolerances. Full-
scale currents other than 1 mA can be chosen, but linearity will
be reduced; 2 mA is the maximum allowable drive. The AD654’s
positive input voltage range spans from –V
S
(ground in sink supply
operation) to four volts below the positive supply. Power sup-
ply rejection degrades as the input exceeds (+V
S
– 3.75 V) and at
(+V
S
– 3.5 V) the output frequency goes to zero.
As indicated by the scaling relationship in Figure 1, a 0.01
µF
timing capacitor will give a 10 kHz full-scale frequency, and
0.001
µF
will give 100 kHz with a 1 mA drive current. Good V/F
linearity requires the use of a capacitor with low dielectric
absorption (DA), while the most stable operation over tempera-
ture calls for a component having a small tempco. Polystyrene,
polypropylene, or Teflon* capacitors are preferred for tempco and
dielectric absorption; other types will degrade linearity. The
capacitor should be wired very close to the AD654. In Figure 1,
Schottky diode CR1 (MBD101) prevents logic common from
dropping more than 500 mV below –V
S
. This diode is not
required if –V
S
is equal to logic common.
In theory, two adjustments calibrate a V/F: scale and offset. In
practice, most applications find the AD654’s 1 mV max voltage
offset sufficiently low to forgo offset calibration. However, the
input amplifier’s 30 nA (typ) bias currents will generate an offset
due to the difference in dc sound resistance between the input
terminals. This offset can be substantial for large values of R
T
=
R1 + R2 and will vary as the bias currents drift over temperature.
Therefore, to maintain the AD654’s low offset, the application may
require balancing the dc source resistances at the inputs (Pins
3 and 4).
For positive inputs, this is accomplished by adding a compensation
resistor nominally equal to R
T
in series with the input as shown
in Figure 3a. This limits the offset to the product of the 30 nA
bias current and the mismatch between the source resistance R
T
and R
COMP
. A second, smaller offset arises from the inputs’ 5 nA
offset current flowing through the source resistance R
T
or R
COMP
.
For negative input voltage and current connections, the compensa-
tion resistor is added at Pin 4 as shown in Figure 3b in lieu of
grounding the pin directly. For both positive and negative inputs,
the use of R
COMP
may lead to noise coupling at Pin 4 and should
therefore be bypassed for lowest noise operation.
(OPTIONAL)
C
V
IN
AD654
R
COMP
R1
R2
Figure 3a. Bias Current Compensation—Positive Inputs
*Teflon is a trademark of E.I. Du Pont de Nemours & Co.
–4–
REV. B
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