AD652
5
6
7
8
5
6
7
8
AD652
SYNCHRONOUS
VOLTAGE-TO-
FREQUENCY
CONVERTER
AD652
SYNCHRONOUS
VOLTAGE-TO-
FREQUENCY
CONVERTER
10kΩ
10kΩ
10kΩ
10kΩ
16kΩ
16kΩ
NC
NC
NC
4kΩ
4kΩ
+
–
9
10
9
10
V
IN
+
–
NC NC
NC
V
IN
A. PLCC 0V TO 10V INPUT
B. PLCC 0V TO 8V INPUT
5
6
7
8
5
6
7
8
AD652
AD652
10kΩ
10kΩ
SYNCHRONOUS
VOLTAGE-TO-
FREQUENCY
CONVERTER
10kΩ
10kΩ
SYNCHRONOUS
VOLTAGE-TO-
FREQUENCY
CONVERTER
16kΩ
16kΩ
NC
+
–
V
IN
NC
5V REF
20
4kΩ
4kΩ
V
9
10
IN
9
10
±5V
NC NC
NC
NC = NO CONNECT
D. PLCC ±5V INPUT
C. PLCC 0V TO 5V INPUT
Figure 13.
PLCC CONNECTIONS
AD652
SYNCHRONOUS
VOLTAGE-TO-
FREQUENCY
CONVERTER
+V
S
The PLCC packaged AD652 offers additional input resistors not
found on the CERDIP-packaged device. These resistors provide
the user with additional input voltage ranges. Besides the 10 V
range available using the on-chip resistor in the CERDIP the
PLCC also offers 8 V and 5 V ranges. Figure 13A to Figure 13C
show the proper connections for these ranges with positive
input voltages. For negative input voltages, the appropriate
resistor should be tied to analog ground and the input voltage
should be applied to Pin 6, the + input of the op amp.
5V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REFERENCE
250kΩ
20kΩ
0.02µF
ONE
SHOT
2MΩ
500Ω
20kΩ
V
1mA
IN
Q
CK
"D"
D
AND
Q FLOP
Bipolar input voltages can be accommodated by injecting
250 µA into Pin 5 with the use of the 5 V reference and the
input resistors. For the 5 V or 2.5 V range, the reference
output, Pin 20, should be tied to Pin 10. The input signal should
then be applied to Pin 8 for a 5 V signal and to Pin 7 for a
2.5 V signal. The input connections for a 5 V range are
shown in Figure 13D. For a 4 V range, the input signal should
be applied to Pin 9, and Pin 20 should be connected to Pin 8.
Figure 14. CERDIP Gain and Offset Trim
350kΩ
3
2
1
20
19
±
3.5mV
500Ω
AD652
OFFSET
TRIM
20kΩ
SYNCHRONOUS
5V
REFERENCE
VOLTAGE-TO-FREQUENCY
CONVERTER
4
5
6
7
8
18
17
16
15
14
0.02µF
GAIN AND OFFSET CALIBRATION
The gain error of the AD652 is laser trimmed to within 0.5%.
If higher accuracy is required, the internal 20 kΩ resistor must
be shunted with a 2 MΩ resistor to produce a parallel equivalent
that is 1% lower in value than the nominal 20 kΩ. Full-scale
adjustment is then accomplished using a 500 Ω series trimmer.
See Figure 14 and Figure 15. When negative input voltages are
used, this 500 Ω trimmer is tied to ground and Pin 6 is the
input pin.
"D"
FLOP
Q
D
AND
10kΩ
Q
CK
2MΩ
10kΩ
ONE
1mA
500Ω
16kΩ
SHOT
V
IN
4kΩ
9
10
11
12
13
Figure 15. PLCC Gain and Offset Trim
Rev. C | Page ±± of 28
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