AD652
The resolution of the A-to-D conversion measurement is
determined by the clock frequency and the gate time. If, for
instance, a resolution of 12 bits is desired and the clock
frequency is 1 MHz (resulting in an AD652 FS frequency of
500 kHz) the gate time is:
ISOLATED FRONT END
In some applications, it may be necessary to have complete
galvanic isolation between the analog signals being measured
and the digital portions of the circuit. The circuit shown in
Figure 32 runs off a single 5 V power supply and provides a self-
contained, completely isolated analog measurement system. The
power for the AD652 SVFC is provided by a chopper and a
transformer, and is regulated to 15 V.
−1
−1
–1
FS Freq
Clock Freq
N
1 MHz
⎛
⎞
⎛
⎞
⎛
⎞
1
2
⎜
⎜
⎟
⎟
⎜
⎜
⎟
⎟
⎜
⎜
⎟
⎟
=
=
N
2 4096
( )
⎝
⎠
⎝
⎠
⎝
⎠
8192
1×106
=
sec = 8.192 ms
Both the chopper frequency and the AD652 clock frequency are
125 kHz, with the clock signal being relayed to the SVFC
through the transformer. The frequency output signal is relayed
through an opto-isolator and latched into a D flop. The chopper
frequency is generated from an AD654 VFC, and is frequency
divided by two to develop differential drive for the chopper
transistors, and to ensure an accurate 50% duty cycle. The pull-
up resistors on the D flop outputs provide a well-defined high
level voltage to the choppers to equalize the drive in each
direction. The 10 µH inductor in the 5 V lead of the transformer
primary is necessary to equalize any residual imbalance in the
drive on each half cycle, and thus prevent saturation of the core.
The capacitor across the primary resonates the system so that
under light loading conditions on the secondary, the wave shape
is sinusoidal and the clock frequency is relayed to the SVFC. To
adjust the chopper frequency, disconnect any load on the
secondary and tune the AD654 for a minimum in the supply
current drawn from the 5 V supply.
Where N is the total number of codes for a given resolution.
Figure 33 shows the AD652 SVFC as an A-to-D converter in
block diagram form.
fOUT
INPUT
V
AD652
COUNTER
GATE
TO µP
IN
CLOCK
÷2N
Figure 33. Block Diagram of SVFC A-to-D Converter
To provide the ÷2N block, a single-chip counter such as the
4020B can be used. The 4020B is a 14-stage binary ripple
counter that has a clock and master reset for inputs, and
buffered outputs from the first stage and the last 11 stages. The
output of the first stage is fCLOCK ÷ 21 = fCLOCK/2, while the output
of the last stage is fCLOCK ÷ 214 = fCLOCK/16384. Therefore, using
this single chip counter as the ÷2N block, 13-bit resolution can
be achieved. Higher resolution can be achieved by cascading D-
type flip flops or another 4020B with the counter.
A-TO-D CONVERSION
In performing an A-to-D conversion, the output pulses of a
VFC are counted for a fixed-gate interval. To achieve maximum
performance with the AD652, the fixed-gate interval should be
generated using a multiple of the SVFC clock input. Counting
in this manner eliminates any errors due to the clock (whether
it be jitter, drift with time or temperature, and so on) since it is
the ratio of the clock and output frequencies that is being
measured.
Table 4 shows the relationship between clock frequency and gate
time for various degrees of resolution. Note that if the variables
are chosen such that the gate times are multiples of 50 Hz,
60 Hz, or 400 Hz, normal mode rejection (NMR) of those line
frequencies occur.
Table 4.
Resolution
N
Clock
Conversion or Gate Time (ms)
Typical Linearity (%)
Comments
12 Bits
12 Bits
12 Bits
4 Digits
14 Bits
14 Bits
14 Bits
4½ Digits
16 Bits
16 Bits
4096
4096
4096
10000
16384
16384
16384
20000
65536
65536
81.92 kHz
2 MHz
4 MHz
200 kHz
327.68 kHz
1.966 MHz
1.638 MHz
400 kHz
655.36 kHz
4 MHz
100
0.002
0.01
0.02
0.002
0.002
0.01
50 Hz, 60 Hz,400 Hz NMR
4.096
2.048
100
100
16.66
20
100
200
32.77
50 Hz, 60 Hz, 400 Hz NMR
50 Hz, 60 Hz, 400 Hz NMR
60 Hz NMR
50 Hz NMR
50 Hz, 60 Hz, 400 Hz NMR
50 Hz, 60 Hz, 400 Hz NMR
0.01
0.002
0.002
0.02
Rev. C | Page 22 of 28
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