AD565A–SPECIFICATIONS
(T = +25 C, V
A
CC
= +15 V, V
EE
= +15 V, unless otherwise noted.)
Min
AD565AK
Typ
Max
Units
Model
DATA INPUTS (Pins 13 to 24)
TTL or 5 Volt CMOS
Input Voltage
Bit ON Logic “1”
Bit OFF Logic “0”
Logic Current (Each Bit)
Bit ON Logic “1”
Bit OFF Logic “0”
RESOLUTION
OUTPUT
Current
Unipolar (All Bits On)
Bipolar (All Bits On or Off)
Resistance (Exclusive of Span Resistors)
Offset
Unipolar
Bipolar (Figure 3, R2 = 50
Ω
Fixed)
Capacitance
Compliance Voltage
T
MIN
to T
MAX
ACCURACY (Error Relative to
Full Scale) +25°C
T
MIN
to T
MAX
DIFFERENTIAL NONLINEARITY
+25°C
T
MIN
to T
MAX
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
TEMPERATURE RANGE
Operating
Storage
POWER REQUIREMENTS
V
CC
, +11.4 to +16.5 V de
V
EE
, –11.4 to –16.5 V dc
POWER SUPPLY GAIN SENSITIVITY
2
V
CC
= +11.4 to +16.5 V dc
V
EE
= –11.4 to –16.5 V dc
PROGRAMMABLE OUTPUT RANGES
(See Figures 2, 3, 4)
1
Min
AD565AJ
Typ
Max
+2.0
+120
+35
+5.5
+0.8
+300
+100
12
+2.0
+120
+35
+5.5
+0.8
+300
+100
12
V
V
µA
µA
Bits
–1.6
0.8
6
–2.0
±
1.0
8
0.01
0.05
25
–2.4
1.2
10
0.05
0.15
+10
–1.6
0.8
6
–2.0
±
1.0
8
0.01
0.05
25
–2.4
1.2
10
0.05
0.1
+10
mA
mA
kΩ
% of F.S. Range
% of F.S. Range
pF
V
LSB
% of F.S. Range
LSB
% of F.S. Range
LSB
–1.5
±
1/4
(0.006)
±
1/2
(0.012)
–1.5
±
1/8
(0.003)
±
1/4
(0.006)
1/2
(0.012)
3/4
(0.018)
1/4
(0.006)
1/2
(0.012)
±
1/2
3/4
MONOTONICITY GUARANTEED
±
1/4
1/2
MONOTONICITY GUARANTEED
1
5
15
2
250
15
30
0
–65
3
–12
3
15
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
±
0.1
±
0.25
±
0.15
15
9.90
1.5
±
0.05
2
10
50
1
5
10
2
250
15
30
0
–65
3
–12
3
15
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
±
0.1
±
0.25
±
0.15
15
9.90
1.5
±
0.05
2
10
20
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ns
ns
ns
°C
°C
mA
mA
ppm of F.S./%
ppm of F.S./%
V
V
V
V
V
400
30
50
+70
+150
5
–18
10
25
400
30
50
+70
+150
5
–18
10
25
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50
Ω
Resistor for R2 (Figure 2)
Bipolar Zero Error with Fixed
50
Ω
Resistor for R1 (Figure 3)
Gain Adjustment Range (Figure 2)
Bipolar Zero Adjustment Range
REFERENCE INPUT
Input Impedance
REFERENCE OUTPUT
Voltage
Current (Available for External Loads)
3
POWER DISSIPATION
0.25
0.15
0.25
±
0.1
% of F.S. Range
% of F.S. Range
% of F.S. Range
% of F.S. Range
kΩ
V
mA
mW
20
10.00
2.5
225
25
10.10
345
20
10.00
2.5
225
25
10.10
345
NOTES
1
The digital inputs are guaranteed but not tested over the operating temperature range.
2
The power supply gain sensitivity is tested in reference to a V
CC
, V
EE
of
±
15 V dc.
3
For operation at elevated temperatures the reference cannot supply current for external loads. It, therefore, should be buffered if additional loads are to be supplied.
Specifications subject to change without notice.
–2–
REV. D
AD [ ANALOG DEVICES ]
