AD538
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
I
1
2
3
4
5
6
7
8
9
18
17
16
15
A
D
Z
V
Z
B
+10V
+2V
I
X
AD538
TOP VIEW
(Not to Scale)
V
X
14 SIGNAL GND
13 PWR GND
+V
S
–V
S
12
11
10
C
V
O
I
Y
I
V
Y
Figure 2. Pin Configuration
Table 3.
Pin No. Mnemonic
Description
1
2
3
IZ
VZ
B
Current Input for the Z Multiplicand.
Voltage Input for the Z Multiplicand.
Output of the Log Ratio Differential Amplifier. This amplifier subtracts the log of the Z input from the log of the X
input, or performs the equivalent logarithmic equivalent of long division.
4
5
6
+10V
+2V
+VS
+10 V Reference Voltage Output.
+2 V Reference Voltage Output.
Positive Supply Rail.
7
–VS
Negative Rail.
8
VO
Output Voltage.
9
I
VY
IY
C
Current Input to the Output Amplifier.
Voltage Input to the Y Multiplicand.
Current Input to the Y Multiplicand.
Current Input to the Base of the Antilog Log-to-Linear Converter.
High level Power Return of the Chip.
10
11
12
13
14
15
16
17
18
PWR GND
SIGNAL GND Low Level Ground Return of the Device.
VX
IX
D
A
Voltage Input of the X Multiplicand.
Current Input of the X Input Multiplicand.
Use for Log Ratio Function.
Use for Log Ratio Function.
Rev. E | Page 6 of 16
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