AD538
TWO-QUADRANT DIVISION
LOG RATIO OPERATION
The two-quadrant linear divider circuit illustrated in Figure 14
uses the same basic connections as the one-quadrant version.
However, in this circuit the numerator has been offset in the
positive direction by adding the denominator input voltage
to it. The offsetting scheme changes the divider’s transfer
function from
Figure 15 shows the AD538 configured for computing the log
of the ratio of two input voltages (or currents). The output
signal from B is connected to the summing junction of the
output amplifier via two series resistors. The 90.9 Ω metal film
resistor effectively degrades the temperature coefficient of the
3500 ppm/°C resistor to produce a 1.09 kΩ +3300 ppm/°C
equivalent value. In this configuration, the VY input must
be tied to some voltage less than zero (−1.2 V in this case)
removing this input from the transfer function.
VZ
VX
VO =10 V
to
The 5 kΩ potentiometer controls the circuit’s scale factor
adjustment providing a +1 V per decade adjustment. The
output offset potentiometer should be set to provide a zero
output with VX = VZ = 1 V. The input V Z adjustment should
be set for an output of 3 V with VZ = l mV and VX = 1 V.
(
VZ + AVX
)
VZ
VX
VO =10V
=10V 1A+
VX
VZ
VX
=10A +10V
–V
S
68kΩ
5%
V
V
Z
where:
V
= 1V LOG
10
O
X
AD589
–1.2V
35kΩ
25kΩ
A=
10MΩ
I
Z
A
D
1
2
3
4
5
6
18
17
16
15
14
13
12
11
1MΩ
48.7Ω
OPTIONAL
INPUT V
V
LOG
25kΩ
Z
RATIO
OS
As long as the magnitude of the denominator input is equal
to or greater than the magnitude of the numerator input, the
circuit accepts bipolar numerator voltages. However, under
the conditions of a 0 V numerator input, the output would
incorrectly equal +14 V. The offset can be removed by connecting
the 10 V reference through Resistors R1 and R2 to the output
section’s summing Node I at Pin 9 thus providing a gain of 1.4
at the center of the trimming potentiometer. The potentiometer,
R2, adjusts out or corrects this offset, leaving the desired
transfer function of 10 V (VZ/VX).
ADJUSTMENT
B
I
X
90.9Ω
V
+10V
+2V
X
V
X
INPUT
1%
25kΩ
100Ω
100Ω
SIGNAL
GND
1k
+3500
ppm/°C
PWR
GND
INTERNAL
VOLTAGE
+15V
–15V
REFERENCE
AD538
OUTPUT
C
7
8
9
OUTPUT
5kΩ 2kΩ
25kΩ
1%
V
O
I
Y
ANTILOG
SCALE
FACTOR
ADJUST
IN4148
V
I
Y
10
LOG
NUMERATOR
DENOMINATOR
25kΩ
V
V
OPTIONAL
Z
X
+V
–V
Z OFFSET TRIM
S
OPTIONAL
10MΩ
–V
S
10kΩ
OUTPUT V
OS
ADJUSTMENT
V
V
Z
S
V
= 10
FOR V ≥ V
X Z
O
68kΩ
35kΩ
X
AD589
Figure 15. Log Ratio Circuit
–1.2V
10MΩ
I
Z
Z
1MΩ
ADJ
1
2
3
4
5
6
18
17
16
15
14
13
12
11
A
D
The log ratio circuit shown achieves 0.5% accuracy in the log
domain for input voltages within three decades of input range:
10 mV to 10 V. This error is not defined as a percent of full-
scale output, but as a percent of input. For example, using a
1 V/decade scale factor, a 1% error in the positive direction
at the input of the log ratio amplifier translates into a 4.3 mV
deviation from the ideal OUTPUT (that is, 1 V × log10 (1.01) =
4.3214 mV). An input error 1% in the negative direction is
slightly different, giving an output deviation of 4.3648 mV.
V
OS
35kΩ
25kΩ
LOG
3.9MΩ
V
RATIO
I
X
B
+10V
V
X
25kΩ
100Ω
100Ω
SIGNAL
GND
+2V
PWR
GND
INTERNAL
VOLTAGE
+15V
REFERENCE
AD538
IN4148
C
7
8
9
–15V
OUTPUT
25kΩ
I
V
Y
O
OUTPUT
ANTILOG
R2
R1
10kΩ 12.4kΩ
V
I
Y
10
LOG
25kΩ
ZERO
ADJUST
Figure 14. Two-Quadrant Division with 10 V Scaling
Rev. E | Page 12 of 16
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