AD5382
HARDWARE FUNCTIONS
RESET FUNCTION
FIFO OPERATION IN PARALLEL MODE
Bringing the
line low resets the contents of all internal
The AD5382 contains a FIFO to optimize operation when
operating in parallel interface mode. The FIFO Enable (level
sensitive, active high) is used to enable the internal FIFO. When
connected to DVDD, the internal FIFO is enabled, allowing the
user to write to the device at full speed. FIFO is only available in
parallel interface mode. The status of the FIFO_EN pin is
sampled on power-up, and after a CLEAR or RESET, to
determine if the FIFO is enabled. In either serial or I2C interface
modes, FIFO_EN should be tied low. Up to 128 successive
instructions can be written to the FIFO at maximum speed in
parallel mode. When the FIFO is full, any further writes to the
device are ignored. Figure 29 shows a comparison between
FIFO mode and non-FIFO mode in terms of channel update
time. Figure 29 also outlines digital loading time.
RESET
registers to their power-on reset state. Reset is a negative edge-
sensitive input. The default corresponds to m at full scale and to
c at zero. The contents of the DAC registers are cleared, setting
VOUT 0 to VOUT 31 to 0 V. This sequence takes 270 µs max.
The falling edge of
low for the duration, returning high when
initiates the reset process;
goes
RESET
BUSY
is complete.
RESET
is low, all interfaces are disabled and all LDAC
While
BUSY
pulses are ignored. When
normal operation and the status of the
until the next falling edge is detected.
returns high, the part resumes
BUSY
pin is ignored
RESET
ASYNCHRONOUS CLEAR FUNCTION
Bringing the
line low clears the contents of the DAC
CLR
registers to the data contained in the user configurable CLR
register and sets VOUT 0 to VOUT 31 accordingly. This func-
tion can be used in system calibration to load zero scale and full
scale to all channels. The execution time for a CLR is 35 µs.
25
WITHOUT FIFO
20
(CHANNEL UPDATE TIME)
AND
FUNCTIONS
LDAC
BUSY
15
is a digital CMOS output that indicates the status of the
BUSY
AD5382. The value of x2, the internal data loaded to the DAC
data register, is calculated each time the user writes new data to
the corresponding x1, c, or m registers. During the calculation
10
WITH FIFO
(CHANNEL UPDATE TIME)
5
of x2, the
output goes low. While
is low, the user
BUSY
BUSY
WITH FIFO
(DIGITAL LOADING TIME)
can continue writing new data to the x1, m, or c registers, but no
DAC output updates can take place. The DAC outputs are
0
1
4
7
10 13 16 19 22 25 28 31 34 37 40
NUMBER OF WRITES
updated by taking the
input low. If
goes low while
LDAC
LDAC
is active, the
update immediately after
event is stored and the DAC outputs
BUSY
LDAC
BUSY
input permanently low, in which case the DAC
Figure 29. Channel Update Rate (FIFO vs. NON-FIFO)
goes high. The user may hold
the
LDAC
POWER-ON RESET
outputs update immediately after
goes high.
also
BUSY
BUSY
goes low during power-on reset and when a falling edge is
detected on the pin. During this time, all interfaces are
The AD5382 contains a power-on reset generator and state
machine. The power-on reset resets all registers to a predefined
state and configures the analog outputs as high impedance. The
pin goes low during the power-on reset sequencing,
preventing data writes to the device.
RESET
disabled and any events on
are ignored. The AD5382
LDAC
BUSY
contains an extra feature whereby a DAC register is not updated
unless its x2 register has been written to since the last time
was brought low. Normally, when
is brought low,
LDAC
LDAC
POWER-DOWN
the DAC registers are filled with the contents of the x2 registers.
However, the AD5382 will only update the DAC register if the
x2 data has changed, thereby removing unnecessary digital
crosstalk.
The AD5382 contains a global power-down feature that puts all
channels into a low power mode and reduces the analog power
consumption to 2 µA max and digital power consumption to
20 µA max. In power-down mode, the output amplifier can be
configured as a high impedance output or provide a 100 kΩ
load to ground. The contents of all internal registers are
retained in power-down mode. When exiting power-down, the
settling time of the amplifier will elapse before the outputs settle
to their correct values.
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