AD5382
ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)
Soft CLR
The AD5382 contains a number of special function registers
(SFRs), as outlined in Table 15. SFRs are addressed with
REG1 = REG0 = 0 and are decoded using address bits A4 to A0.
REG1 = REG0 = 0, A4–A0 = 00010
DB13–DB0 = Don’t Care.
Executing this instruction performs the CLR, which is function-
Table 15. SFR Register Functions (REG1 = 0, REG0 = 0)
ally the same as that provided by the external
pin. The
CLR
R/W
A4 A3 A2 A1 A0 Function
DAC outputs are loaded with the data in the CLR code register.
It takes 35 µs to fully execute the SOFT CLR and is indicated by
X
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
NOP (No Operation)
Write CLR Code
Soft CLR
Soft Power-Down
Soft Power-Up
Control Register Write
Control Register Read
Monitor Channel
Soft Reset
the
low time.
BUSY
Soft Power-Down
REG1 = REG0 = 0, A4–A0 = 01000
DB13–DB0 = Don’t Care
Executing this instruction performs a global power-down
feature that puts all channels into a low power mode that
reduces the analog supply current to 2 µA max and the digital
current to 20 µA max. In power-down mode, the output
amplifier can be configured as a high impedance output or
provide a 100 kΩ load to ground. The contents of all internal
registers are retained in power-down mode. No register can be
written to while in power-down.
SFR COMMANDS
NOP (No Operation)
REG1 = REG0 = 0, A4–A0 = 00000
Performs no operation but is useful in serial readback mode to
Soft Power-Up
clock out data on DOUT for diagnostic purposes.
pulses
BUSY
REG1 = REG0 = 0, A4–A0 = 01001
DB13–DB0 = Don’t Care
low during a NOP operation.
Write CLR Code
This instruction is used to power up the output amplifiers and
the internal reference. The time to exit power–down is 8 µs. The
hardware power-down and software function are internally
combined in a digital OR function.
REG1 = REG0 = 0, A4–A0 = 00001
DB13–DB0 = Contain the CLR data
Bringing the
line low or exercising the soft clear function
CLR
Soft RESET
will load the contents of the DAC registers with the data con-
tained in the user configurable CLR register, and will set
VOUT0 to VOUT31 accordingly. This can be very useful for
setting up a specific output voltage in a clear condition. It is also
beneficial for calibration purposes; the user can load full scale
or zero scale to the clear code register and then issue a hard-
ware or software clear to load this code to all DACs, removing
the need for individual writes to each DAC. Default on power-
up is all zeros.
REG1 = REG0 = 0, A4–A0 = 01111
DB13–DB0 = Don’t Care
This instruction is used to implement a software reset. All
internal registers are reset to their default values, which
correspond to m at full scale and c at zero. The contents of the
DAC registers are cleared, setting all analog outputs to 0 V. The
soft reset activation time is 135 µs max.
Rev. 0 | Page 22 of 40
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