AD1885
tRST_LOW
tRST2CLK
BIT_CLK
SYNC
RESET
tRISECLK
tFALLCLK
tFALLSYNC
tFALLDIN
BIT_CLK
Figure 1. Cold Reset
tRISESYNC
SDATA_IN
tRISEDIN
tRST2CLK
tSYNC_HIGH
SYNC
BIT_CLK
SDATA_OUT
tRISEDOUT
tFALLDOUT
Figure 2. Warm Reset
Figure 5. Signal Rise and Fall Time
tCLK_LOW
SLOT 2
SLOT 1
SYNC
BIT_CLK
tCLK_HIGH
tCLK_PERIOD
BIT_CLK
tSYNC_LOW
WRITE
TO 0x26
DATA
PR4
DON’T
CARE
SDATA_OUT
SDATA_IN
SYNC
tS2_PDOWN
tSYNC_HIGH
tSYNC_PERIOD
NOTE: BIT_CLK NOT TO SCALE
Figure 3. Clock Timing
Figure 6. AC-Link Low Power Mode Timing
tSETUP
RESET
BIT_CLK
SYNC
SDATA_OUT
tSETUP2RST
SDATA_OUT
SDATA_IN, BIT_CLK
HI-Z
tHOLD
tOFF
Figure 4. Data Setup and Hold
Figure 7. ATE Test Mode
REV. 0
–6–
ADI [ ADI ]
