AD1885
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
Min
Typ
Max
Unit
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Startup Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Startup Delay
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter*
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
tRST_LOW
tRST2CLK
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
1.0
µs
162.8
ns
µs
1.3
19.5
µs
162.8
ns
MHz
ns
ps
ns
ns
kHz
µs
12.288
81.4
tCLK_PERIOD
750
48.84
48.84
tCLK_HIGH
tCLK_LOW
32.56
32.56
42
38
48.0
20.8
2.5
SYNC Period
tSYNC_PERIOD
tSETUP
tHOLD
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
5
5
2
2
2
2
2
2
2
2
0
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
tS2_PDOWN
tSETUP2RST
tOFF
4
4
4
4
4
4
4
4
10
10
10
10
10
10
10
10
10
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)
Rising Edge of RESET to HI-Z Delay
Propagation Delay
RESET Rise Time
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
25
15
50
15
NOTES
*Output jitter is directly dependent on crystal input jitter.
Specifications subject to change without notice.
REV. 0
–5–
ADI [ ADI ]
