AD1885
Extended Audio Status and Control Register (Index 2Ah)
Reg
Name
D15 D14 D13 D12 D11 D10 D9
D8
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
Default
Num
2Ah Extended Audio St/Ctrl
X
X
X
X
X
X
X
VRA 0000h
Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio
features.
VRA
Variable Rate Audio. VRA = 1 enables support for Variable Rate Audio mode (sample rate control registers and
SLOTREQ signaling).
PCM DAC Rate Register (Index 2Ch)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
2Ch/(7Ah) PCM DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample
rates are reset to 48 kHz.
SR[15:0]
Writing to this register allows programming of the sampling frequency from 7040 Hz (1B80h) to 48 kHz (BB80h)
in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (BB80h) causes the
codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back
when read, otherwise the closest rate supported is returned.
PCM ADC Rate Register (Index 32h)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
32h/(78h) PCM ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample
rates are reset to 48 kHz.
SR[15:0]
Writing to this register allows programming of the sampling frequency from 7040 Hz (1B80h) to 48 kHz (BB80h)
in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (BB80h) causes the
codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back
when read; otherwise, the closest rate supported is returned.
Jack Sense/Audio Interrupt/Status Register (Index 72h)
Reg
Num
Name
D15
D14
D13
D12
D11 D10 D9
D8 D7
JS0 JS1
D6
D5
D4
D3
D2 D1 D0
Default
0000h
Jack Sense/Audio JS1_OUT/ JS0_
Interrupt/Status FUNCT
JS1
JS0
JS1_ JS0_ JS1
JS0
JS1
JS0
AUD
JS
72h
JS1 JS0
OUT PUDIS PUDIS OE OE DIS DIS CLR CLR MODE MODE INT
INT
Note: all register bits are read/write except for AUDINT, JSINT, JS0 and JS1, which are read only.
JSINT
Indicates that a jack sense interrupt has been generated by JS0 or JS1. Remains set until all JS enabled interrupts
are cleared.
JS0
Indicates Pin JS0 state.
JS1
Indicates Pin JS1 state.
AUDINT
JS0MODE
JS1MODE
JS0CLR
Indicates the Codec has generated audio interrupt. Remains set until software clears all pending interrupts.
Sets JS0 pin input mode, 1 = Interrupt 0 = Jack Sense.
Sets JS1 pin input mode, 1 = Interrupt 0 = Jack Sense.
This bit is set by the Codec when there is a pending JS0 interrupt. Software must clear this bit to clear the JS0
interrupt status bit.
JS1CLR
This bit is set by the Codec when there is a pending JS1 interrupt. Software must clear this bit to clear the JS1
interrupt status bit.
JS0DIS
JS1DIS
If the JS0DIS bit is set, the Codec ignores Jack Sense pin JS0.
If the JS1DIS bit is set, the Codec ignores Jack Sense pin JS1.
REV. 0
–19–
ADI [ ADI ]
