AD1819B
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
Min
Typ
Max
Units
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Start-Up Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Start-Up Delay
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter*
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
tRST_LOW
tRST2CLK
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
1.0
162.8
0.0814
µs
ns
µs
1.3
19.5
µs
162.8
ns
MHz
ns
ps
ns
ns
kHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
12.288
81.4
tCLK_PERIOD
750
48.84
48.84
tCLK_HIGH
tCLK_LOW
32.56
32.56
40.7
40.7
48.0
20.8
SYNC Period
tSYNC_PERIOD
tSETUP
tHOLD
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
15.0
15.0
tRISE CLK
tFALL CLK
tRISE SYNC
tFALL SYNC
tRISE DIN
tFALL DIN
tRISE DOUT
tFALL DOUT
tS2_PDOWN
4
4
4
4
4
4
4
4
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to
SYNC, SDATA_OUT)
1.0
25
tSETUP2RST
tOFF
15
ns
ns
Rising Edge of RESET to HI-Z Delay
*Output Jitter is directly dependent on crystal input jitter.
tRST_LOW
tRST2CLK
RESET
BIT_CLK
Figure 1. Cold Reset
tRST2CLK
tSYNC_HIGH
SYNC
BIT_CLK
Figure 2. Warm Reset
tCLK_LOW
BIT_CLK
tCLK_HIGH
tCLK_PERIOD
tSYNC_LOW
SYNC
tSYNC_HIGH
tSYNC_PERIOD
Figure 3. Clock Timing
REV. 0
–6–
ADI [ ADI ]
