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7447797470 参数 Datasheet PDF下载

7447797470图片预览
型号: 7447797470
PDF下载: 下载PDF文件 查看货源
内容描述: 双5 A, 20 V同步降压型 [Dual 5 A, 20 V Synchronous Step-Down]
分类和应用:
文件页数/大小: 32 页 / 831 K
品牌: ADI [ ADI ]
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Data Sheet  
ADP2325  
To meet the 5% overshoot and undershoot requirement, use  
the following equation to calculate the capacitance:  
Figure 52 shows the 1.2 V rail bode plot at 5 A. The cross  
frequency is 42 kHz and the phase margin is 50°.  
60  
180  
144  
108  
72  
K
OV ×ISTEP 2 ×L  
COUT_OV  
=
=
48  
36  
(
VOUT + ∆VOUT _OV  
)
2VOUT  
2
KUV × ∆ISTEP 2 × L  
24  
COUT_UV  
2×  
(
VIN VOUT × ∆VOUT _UV  
)
12  
36  
For estimation purposes, use KOV = KUV = 2. For VOUT1 = 1.2 V,  
use COUT_OV1 = 188 µF and COUT_UV1 = 21 µF. For VOUT2 = 3.3 V,  
use COUT_OV2 = 55 µF and COUT_UV2 = 21 µF.  
0
0
–12  
–24  
–36  
–48  
–60  
–36  
–72  
–108  
–144  
–180  
For the 1.2 V rail, ESR of the output capacitor must be smaller  
than 8.3 mΩ, and the output capacitance must be larger than  
188 µF. It is recommend that three 100 µF, X5R, 6.3 V ceramic  
capacitors be used, such as the GRM32ER60J107ME20 from  
Murata, with an ESR = 2 mΩ.  
1
2
1k  
10k  
100k  
FREQUENCY (Hz)  
1M  
Figure 52. Bode Plot for 1.2 V Rail  
For the 3.3 V rail, the ESR of the output capacitor must be  
smaller than 23 mΩ, and the output capacitance must be  
larger than 55 µF. It is recommended that two 47 µF, X5R,  
6.3 V ceramic capacitors be used, such as the Murata  
GRM32ER60J476ME20, with an ESR = 2 mΩ.  
For the 3.3 V rail, the 47 µF ceramic output capacitor has a  
derated value of 32 µF.  
2×π ×3.3V×2×32 μF×50 kHz  
RC2  
CC2  
CCP2  
=
= 26.5 kΩ  
0.6 V×500 μS×8.33 A/V  
0.66Ω + 0.001Ω ×2×32μF  
26.5kΩ  
LOW-SIDE MOSFET SELECTION  
(
)
=
=
1594pF  
A low RDSON N-channel MOSFET is selected for high efficiency  
solutions. The MOSFET breakdown voltage must be greater  
than 1.2 V × VIN, and the drain current must be greater than  
0.001 Ω×2×32μF  
=
= 2.4 pF  
1.2 V × ILIMIT  
.
26.5kΩ  
It is recommended that a 30 V, N-channel MOSFET be used, such  
as the FDS8880 from Fairchild. The RDSON of the FDS8880 at a  
4.5 V driver voltage is 12 mΩ, and the total gate charge is 12 nC.  
By using standard component values of RC2 = 27 kΩ and  
C2 = 1500 pF, no CCP2 is needed.  
C
Figure 53 shows the 3.3 V rail bode plot at 5 A. The cross  
frequency is 55 kHz and phase margin is 67°.  
COMPENSATION COMPONENTS  
60  
180  
144  
108  
72  
For better load transient and stability performance, set the  
cross frequency, fC, to fSW/10. In this case, fSW runs at 500 kHz;  
therefore, the fC is set to 50 kHz.  
48  
36  
For the 1.2 V rail, the 100 µF ceramic output capacitor has  
a derated value of 64 µF.  
24  
12  
36  
2×π ×1.2V ×3×64 μF×50 kHz  
0
0
RC1  
CC1  
=
=
= 28.9 kΩ  
0.6 V  
0.24Ω + 0.001Ω  
28.9kΩ  
×
500 μS  
×
8.33 A/V  
–12  
–24  
–36  
–48  
–60  
–36  
–72  
–108  
–144  
–180  
(
)
×3×64μF  
= 1598pF  
0.001Ω×3×64μF  
CCP1  
=
= 6.6pF  
1
2
1k  
10k  
100k  
FREQUENCY (Hz)  
1M  
28.9kΩ  
By choosing standard components where RC1 = 28 kΩ and CC1  
1500 pF, no CCP1 is needed.  
=
Figure 53. Bode Plot for 3.3 V Rail  
Rev. 0 | Page 25 of 32  
 
 
 
 
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