AD585
LOGIC INPUT
ence between the voltage being measured and the voltage previ-
ously measured determines the fraction by which the
dielectric absorption figure is multiplied. It is impossible to
readily correct for this error source. The only solution is to use a
capacitor with dielectric absorption less than the maximum
tolerable error. Capacitor types such as polystyrene, polypropy-
lene or Teflon are recommended.
The sample-and-hold logic control was designed for versatile
logic interfacing. The HOLD and HOLD inputs may be used
with both low and high level CMOS, TTL and ECL logic sys-
tems. Logic threshold programmability was achieved by using a
differential amplifier as the input stage for the digital inputs. A
predictable logic threshold may be programmed by referencing
either HOLD or HOLD to the appropriate threshold voltage.
For example, if the internal 1.4 V reference is applied to HOLD
an input signal to HOLD between +1.8 V and +VS will place
the AD585 in the hold mode. The AD585 will go into the
sample mode for this case when the input is between –VS and
+1.0 V. The range of references which may be applied is from
(–VS +4 V) to (+VS –3 V).
GROUNDING
Many data-acquisition components have two or more ground
pins which are not connected together within the device. These
“grounds” are usually referred to as the Logic Power Return
Analog Common (Analog Power Return), and Analog Signal
Ground. These grounds must be tied together at one point,
usually at the system power-supply ground. Ideally, a single
solid ground would be desirable. However, since current flows
through the ground wires and etch stripes of the circuit cards,
and since these paths have resistance and inductance, hundreds
of millivolts can be generated between the system ground point
and the ground pin of the AD585. Separate ground returns
should be provided to minimize the current flow in the path
from sensitive points to the system ground point. In this way
supply currents and logic-gate return currents are not summed
into the same return path as analog signals where they would
cause measurement errors.
OPTIONAL CAPACITOR SELECTION
If an additional capacitor is going to be used in conjunction
with the internal 100 pF capacitor it must have a low dielectric
absorption. Dielectric absorption is just that; it is the charge
absorbed into the dielectric that is not immediately added to or
removed from the capacitor when rapidly charged or discharged.
The capacitor with dielectric absorption is modeled in Figure 14.
Figure 14. Capacitor Model with Dielectric Absorption
If the capacitor is charged slowly, CDA will eventually charge to
the same value as C. But unfortunately, good dielectrics have
very high resistances, so while CDA may be small, RX is large and
the time constant RX CDA typically runs into the millisecond
range. In fast charge, fast-discharge situations the effect of di-
electric absorption resembles “memory”. In a data acquisition
system where many channels with widely varying data are being
sampled the effect is to have an ever changing offset which ap-
pears as a very nonlinear sample-to-hold offset since the differ-
Figure 15. Basic Grounding Practice
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Terminal PLCC (P-20A)
20-Terminal LCC (E-20A)
14-Pin Cerdip (Q-14)
–6–
REV. A
ADI [ ADI ]
