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5962-9581501HXX 参数 Datasheet PDF下载

5962-9581501HXX图片预览
型号: 5962-9581501HXX
PDF下载: 下载PDF文件 查看货源
内容描述: [IC DUAL 3-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68, CERAMIC, LCC-68, Analog to Digital Converter]
分类和应用: 转换器模数转换器
文件页数/大小: 16 页 / 253 K
品牌: ADI [ ADI ]
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AD10242  
O ver voltage Recover y Tim e  
D EFINITIO N O F SP ECIFICATIO NS  
Analog Bandwidth  
T he analog input frequency at which the spectral power of the  
fundamental frequency (as determined by the FFT analysis) is  
reduced by 3 dB.  
T he amount of time required for the converter to recover to  
0.02% accuracy after an analog input signal of the specified per-  
centage of full scale is reduced to midscale.  
P ower Supply Rejection Ratio  
T he ratio of a change in input offset voltage to a change in  
power supply voltage.  
Aper tur e D elay  
T he delay between the 50% point of the rising edge of the  
ENCODE command and the instant at which the analog input  
is sampled.  
Signal-to-Noise-and-D istor tion (SINAD )  
T he ratio of the rms signal amplitude (set at 1 dB below full  
scale) to the rms value of the sum of all other spectral compo-  
nents, including harmonics but excluding dc.  
Aper tur e Uncer tainty (Jitter )  
T he sample-to-sample variation in aperture delay.  
Signal-to-Noise Ratio (without H ar m onics)  
D iffer ential Nonlinear ity  
T he ratio of the rms signal amplitude (set at 1 dB below full  
scale) to the rms value of the sum of all other spectral compo-  
nents, excluding the first five harmonics and dc.  
T he deviation of any code from an ideal 1 LSB step.  
Encode P ulse Width/D uty Cycle  
Pulse width high is the minimum amount of time that the  
ENCODE pulse should be left in logic “1” state to achieve rated  
performance; pulse width low is the minimum time ENCODE  
pulse should be left in low state. At a given clock rate, these  
specs define an acceptable Encode duty cycle.  
Spur ious-Fr ee D ynam ic Range  
T he ratio of the rms signal amplitude to the rms value of the  
peak spurious spectral component. T he peak spurious compo-  
nent may or may not be a harmonic. May be reported in dBc  
(i.e., degrades as signal levels is lowered) or in dBFS (always re-  
lated back to converter full scale).  
H ar m onic D istor tion  
T he ratio of the rms signal amplitude to the rms value of the  
worst harmonic component.  
Tr ansient Response  
T he time required for the converter to achieve 0.02% accuracy  
when a one-half full-scale step function is applied to the analog  
input.  
Integr al Nonlinear ity  
T he deviation of the transfer function from a reference line mea-  
sured in fractions of 1 LSB using a “best straight line” deter-  
mined by a least square curve fit.  
Two-Tone Inter m odulation D istor tion Rejection  
T he ratio of the rms value of either input tone to the rms value  
of the worst third order intermodulation product; reported in  
dBc.  
Minim um Conver sion Rate  
T he encode rate at which the SNR of the lowest analog signal  
frequency drops by no more than 3 dB below the guaranteed  
limit.  
Two-Tone SFD R  
T he ratio of the rms value of either input tone to the rms value  
of the peak spurious component. T he peak spurious compo-  
nent may or may not be an IMD product. May be reported  
in dBc (i.e., degrades as signal levels is lowered) or in dBFS  
(always related back to converter full scale).  
Maxim um Conver sion Rate  
T he encode rate at which parametric testing is performed.  
O utput P r opagation D elay  
The delay between the 50% point of the rising edge of ENCODE  
command and the time when all output data bits are within  
valid logic levels.  
REV. A  
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