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5962-9581501HXX 参数 Datasheet PDF下载

5962-9581501HXX图片预览
型号: 5962-9581501HXX
PDF下载: 下载PDF文件 查看货源
内容描述: [IC DUAL 3-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68, CERAMIC, LCC-68, Analog to Digital Converter]
分类和应用: 转换器模数转换器
文件页数/大小: 16 页 / 253 K
品牌: ADI [ ADI ]
 浏览型号5962-9581501HXX的Datasheet PDF文件第1页浏览型号5962-9581501HXX的Datasheet PDF文件第2页浏览型号5962-9581501HXX的Datasheet PDF文件第4页浏览型号5962-9581501HXX的Datasheet PDF文件第5页浏览型号5962-9581501HXX的Datasheet PDF文件第6页浏览型号5962-9581501HXX的Datasheet PDF文件第7页浏览型号5962-9581501HXX的Datasheet PDF文件第8页浏览型号5962-9581501HXX的Datasheet PDF文件第9页  
AD10242  
Test  
Level  
Mil  
Subgroup  
AD 10242BZ/TZ  
Typ  
P aram eter  
Tem p  
Min  
Max  
Units  
SPURIOUS-FREE DYNAMIC RANGE9  
Analog Input @ 1.2 MHz  
@ 4.85 MHz  
+25°C  
+25°C  
Full  
+25°C  
Full  
I
I
II  
I
II  
I
81  
80  
79  
70  
69  
67  
66  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
4
5, 6  
4
5, 6  
4
5, 6  
70  
70  
63  
63  
60  
60  
@ 9.9 MHz  
@ 19.5 MHz  
+25°C  
Full  
II  
T WO-T ONE IMD REJECT ION 10  
F1, F2 @ –7 dBFS  
Full  
II  
4, 5, 6  
12  
70  
75  
76  
80  
10  
dBc  
dB  
ns  
CHANNEL-TO-CHANNEL ISOLAT ION11  
T RANSIENT RESPONSE  
+25°C  
+25°C  
IV  
V
LINEARIT Y  
Differential Nonlinearity  
(Encode = 20 MHz)  
Integral Nonlinearity  
+25°C  
Full  
+25°C  
Full  
IV  
IV  
V
12  
12  
0.3  
0.5  
0.3  
0.5  
1.0  
1.25  
LSB  
LSB  
LSB  
LSB  
(
Encode = 20 MHz)  
V
OVERVOLT AGE RECOVERY T IME12  
VIN = 2.0 × FS  
VIN = 4.0 × FS  
Full  
Full  
IV  
IV  
12  
12  
50  
75  
100  
200  
ns  
ns  
DIGIT AL OUT PUT S  
Logic Compatibility  
Logic “1” Voltage13  
Logic “0” Voltage14  
Output Coding  
CMOS  
4.2  
0.45  
Full  
Full  
I
I
1, 2, 3  
1, 2, 3  
3.5  
V
V
0.65  
T wos Complement  
POWER SUPPLY  
AVCC Supply Voltage  
I (AVCC) Current  
AVEE Supply Voltage  
I (AVEE) Current  
DVCC Supply Voltage  
I (DVCC) Current  
ICC (T otal) Supply Current  
Power Dissipation (T otal)  
Power Supply Rejection Ratio (PSRR)  
Pass Band Ripple to 10 MHz  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
VI  
V
VI  
V
VI  
V
I
I
I
IV  
+5.0  
260  
–5.0  
55  
+5.0  
25  
350  
1.75  
0.01  
V
mA  
V
mA  
V
mA  
mA  
W
1, 2, 3  
1, 2, 3  
7, 8  
400  
2.0  
0.02  
0.2  
% FSR/% VS  
dB  
12  
NOT ES  
1 Gain tests are performed on AIN3 over specified input voltage range.  
2 Input capacitance specifications combines AD9631 die capacitance + ceramic package capacitance.  
3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.  
4 ENCODE (Pin 4) driven by single-ended source; ENCODE (Pin 5) bypassed to ground through 0.01 µF capacitor.  
5 ENCODE (Pin 4) may also be driven differentially in conjunction with ENCODE (Pin 5); see “Encoding the AD10242” for details.  
6 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.  
7 Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 40.0 MSPS.  
8 Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 40.0 MSPS.  
9 Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur.  
10 Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst 3rd order intermod product. f1 = 10.0 MHz  
± 100 kHz, 50 kHz f1 – f2 300 kHz.  
11 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel (AIN1).  
12 Input driven to 2× and 4× AIN1 range for >4 clock cycles. Output recovers inband in specified time with Encode = 40 MSPS. No foldover guaranteed.  
13 Outputs are sourcing 10 µA.  
14 Outputs are sinking 10 µA.  
All specifications guaranteed within 100 ms of initial power up regardless of sequencing.  
Specifications subject to change without notice.  
REV. A  
–3–