AD7893
CONVST
600ns MIN
SCLK
tCONVERT
CONVERSION IS INITIATED
AND TRACK/HOLD GOES
INTO HOLD
µP INT SERVICE
OR POLLING
ROUTINE
SERIAL READ
OPERATION
READ OPERATION
SHOULD END 600ns
PRIOR TO NEXT
CONVST INDICATES
TO µP THAT
CONVERSION IS
COMPLETE
RISING EDGE OF
CONVST
Figure 4. CONVST Used as Status Signal
This scheme limits the throughput rate to 12 µs minimum; how-
ever, depending on the response time of the microprocessor to
the interrupt signal and the time taken by the processor to read
the data, this may be the fastest the system could have operated.
In any case, the CONVST signal does not have to have a 50:50
duty cycle. This can be tailored to optimize the throughput rate
of the part for a given system.
clock, the AD7893 will start over again with outputting data
from its output register, and the data bus will no longer be
three-stated even when the clock stops. Provided that the serial
clock has stopped before the next falling edge of CONVST, the
AD7893 will continue to operate correctly with the output shift
register being reset on the falling edge of CONVST; however,
the SCLK line must be low when CONVST goes low in order
to reset the output shift register correctly.
Alternatively, the CONVST signal can be used as a normal narrow
pulse width. The rising edge of CONVST can be used as an active
high or rising edge-triggered interrupt. A software delay of 6 µs can
then be implemented before data is read from the part.
The serial clock input does not have to be continuous during the
serial read operation. The sixteen bits of data (four leading zeros
and 12 bit conversion result) can be read from the AD7893 in a
number of bytes; however, the SCLR input must remain low be-
tween the two bytes.
Serial Interface
The serial interface to the AD7893 consists of just two wires, a
serial clock input (SCLK) and the serial data output (SDATA).
This allows for an easy to use interface to most microcontrollers,
DSP processors and shift registers.
Normally, the output register is updated at the end of conver-
sion. If a serial read from the output register is in progress when
conversion is complete; however, the updating of the output
register is deferred. In this case, the output register is updated
when the serial read is completed. If the serial read has not been
completed before the next falling edge of CONVST, the output
register will be updated on the falling edge of CONVST, and
the output shift register count is reset. In applications where the
data read has been started and not completed before the falling
edge of CONVST, the user must provide a CONVST pulse
width of greater than 1.5 µs to ensure correct setup of the AD7893
before the next conversion is initiated. In applications where the
output update takes place either at the end of conversion or at
the end of a serial read that is completed 1.5 µs before the rising
edge of CONVST, the normal pulse width of 50 ns minimum
applies to CONVST.
Figure 5 shows the timing diagram for the read operation to the
AD7893. The serial clock input (SCLK) provides the clock
source for the serial interface. Serial data is clocked out from the
SDATA line on the rising edge of this clock and is valid on the
falling edge of SCLK. Sixteen clock pulses must be provided to
the part to access to full conversion result. The AD7893 pro-
vides four leading zeros followed by the 12-bit conversion result
starting with the MSB (DB11). The last data bit to be clocked
out on the final rising clock edge is the LSB (DB0). On the six-
teenth falling edge of SCLK, the SDATA line is disabled (three-
stated). After this last bit has been clocked out, the SCLK input
should return low and remain low until the next serial data read
operation. If there are extra clock pulses after the sixteenth
t2
SCLK (I)
t3
t5
DB0
t4
THREE-STATE
THREE-STATE
SDATA (O)
DB11
DB10
FOUR LEADING ZEROS
Figure 5. Data Read Operation
–8–
REV. E
ADI [ ADI ]
