AD7837/AD7847
UNIPOLAR BINARY OPERATION
A0/A1
ADDRESS DATA
t6 t7
Figure 15 shows DAC A on the AD7837/AD7847 connected
for unipolar binary operation. Similar connections apply for
DAC B. When VIN is an ac signal, the circuit performs 2-quad-
rant multiplication. The code table for this circuit is shown in
Table III. Note that on the AD7847 the feedback resistor RFB is
CS
t1
t2
t3
internally connected to VOUT
.
WR
V
DD
t5
t4
VALID
V
AD7837
AD7847
DD
R
FBA
*
DATA
DATA
V
V
OUTA
REFA
DAC A
DGND AGNDA
V
OUT
t8
V
IN
LDAC
V
*INTERNALLY
CONNECTED
ON AD7847
SS
Figure 14. AD7837 Write Cycle Timing Diagram
V
SS
Figure 15. Unipolar Binary Operation
CS, WR, A0 and A1 control the loading of data to the input
latches. The eight data inputs accept right-justified data. Data
can be loaded to the input latches in any sequence. Provided that
LDAC is held high, there is no analog output change as a result
of loading data to the input latches. Address lines A0 and A1
determine which latch data is loaded to when CS and WR are low.
The control logic truth table for the part is shown in Table II.
Table III. Unipolar Code Table
DAC Latch Contents
MSB LSB
Analog Output, VOUT
4095
–VIN
–VIN
×
×
×
1111 1111 1111
4096
Table II. AD7837 Truth Table
2048
CS WR A1 A0 LDAC Function
= –1/2 VIN
1000 0000 0000
4096
1
X
0
0
0
0
1
X
1
0
0
0
0
1
X
X
0
0
1
1
X
X
X
0
1
0
1
X
1
1
1
1
1
1
0
No Data Transfer
No Data Transfer
1
–VIN
DAC A LS Input Latch Transparent
DAC A MS Input Latch Transparent
DAC B LS Input Latch Transparent
DAC B MS Input Latch Transparent
DAC A and DAC B DAC Latches
Updated Simultaneously from the
Respective Input Latches
0000 0000 0001
0000 0000 0000
4096
0 V
VIN
Note 1 LSB =
4096
.
X = Don’t Care.
The LDAC input controls the transfer of 12-bit data from the
input latches to the DAC latches. When LDAC is taken low, both
DAC latches, and hence both analog outputs, are updated at
the same time. The data in the DAC latches is held on the rising
edge of LDAC. The LDAC input is asynchronous and indepen-
dent of WR. This is useful in many applications especially in the
simultaneous updating of multiple AD7837s. However, care must
be taken while exercising LDAC during a write cycle. If an LDAC
operation overlaps a CS and WR operation, there is a possibility
of invalid data being latched to the output. To avoid this, LDAC
must remain low after CS or WR return high for a period equal
to or greater than t8, the minimum LDAC pulsewidth.
–8–
REV. C
ADI [ ADI ]
