AD7837/AD7847
AD7837–6502/6809 Interface
Figure 25 shows an interface between the AD7837 and the 6502
or 6809 microprocessor. For the 6502 microprocessor, the φ2
clock is used to generate the WR, while for the 6809 the E sig-
nal is used.
A15
ADDRESS BUS
A0
A0 A1
ADDRESS
DECODE
6502/6809
R/W
CS
LDAC
EN
AD7837
*
ꢃ2 OR E
WR
DB7
DB0
D7
D0
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. AD7837 to 6502/6809 Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Plastic DIP (N-24)
24-Lead Cerdip (Q-24)
1.228 (31.19)
1.226 (31.14)
24
13
0.295
PIN 1
(7.493)
24
13
12
0.261 ꢀ 0.001
(6.61 ꢀ 0.03)
0.320 (8.128)
0.290 (7.366)
MAX
1
12
0.32 (8.128)
0.30 (7.62)
1
0.070 (1.778)
0.020 (0.508)
1.290 (32.77) MAX
PIN 1
0.180
(4.572)
MAX
0.225 (5.715)
0.130 (3.30)
0.128 (3.25)
MAX
0.125 (3.175)
MIN
SEATING
PLANE
SEATING
PLANE
0.012 (0.305)
0.008 (0.203)
TYP
0.011 (0.28)
0.009 (0.23)
0.021 (0.533) 0.110 (2.794)
0.015 (0.381) 0.090 (2.286)
0.065 (1.651)
0.055 (1.397)
15°
0°
0.02 (0.5)
0.016 (0.41)
0.11 (2.79)
0.09 (2.28)
0.07 (1.78)
0.05 (1.27)
15°
0°
TYP
TYP
1. LEAD NO. 1 IDENTIFIED BY A DOT OR NOTCH.
2. PLASTIC LEADS WILL EITHER BE SOLDER DIPPED OR TIN LEAD PLATED.
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
1. LEAD NO. 1 IDENTIFIED BY A DOT OR NOTCH.
2. CERDIP LEADS WILL EITHER BE TIN PLATED OR SOLDER DIPPED.
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
24-Lead SOIC (R-24)
0.608 (15.45)
0.596 (15.13)
24
1
13
12
0.299 (7.6)
0.291 (7.39)
0.414 (10.52)
0.398 (10.10)
PIN 1
0.096 (2.44)
0.089 (2.26)
0.03 (0.76)
0.02 (0.51)
6ꢄ
0ꢄ
0.05
(1.27)
SEATING
PLANE
0.019 (0.49)
0.014 (0.35)
0.01 (0.254)
0.006 (0.15)
0.042 (1.067)
0.018 (0.457)
0.013 (0.32)
0.009 (0.23)
1. LEAD NO. 1 IDENTIFIED BY A DOT.
2. SOIC LEADS WILL EITHER BE TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
–12–
REV. C
ADI [ ADI ]
