AD7837/AD7847–SPECIFICATIONS1
(VDD = +15 V ꢀ 5%, VSS = –15 V ꢀ 5%, AGNDA = AGNDB = DGND
= O V. VREFA = VREFB = +10 V, RL = 2 kꢁ, CL = 100 pF [VOUT connected to RFB AD7837]. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
A Version
B Version
S Version
Units
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
12
1
1
12
1/2
1
12
1
1
Bits
LSB max
LSB max
Relative Accuracy2
Differential Nonlinearity2
Zero Code Offset Error2
@ +25°C
Guaranteed Monotonic
2
4
2
3
2
4
mV max
mV max
DAC Latch Loaded with All 0s
Temperature Coefficient = 5 µV/°C typ
TMIN to TMAX
Gain Error2
@ +25°C
TMIN to TMAX
4
5
2
3
4
5
LSB max
LSB max
DAC Latch Loaded with All 1s
Temperature Coefficient = 2 ppm of
FSR/°C typ
REFERENCE INPUTS
VREF Input Resistance
VREFA, VREFB Resistance Matching
8/13
2
8/13
2
8/13
2
kΩ min/max
% max
Typical Input Resistance = 10 kΩ
Typically 0.25%
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
1
2.4
0.8
1
2.4
0.8
1
V min
V max
µA max
pF max
Digital Inputs at 0 V and VDD
VOUT Connected to AGND
Input Capacitance3
8
8
8
ANALOG OUTPUTS
DC Output Impedance
Short Circuit Current
0.2
11
0.2
11
0.2
11
Ω typ
mA typ
POWER REQUIREMENTS4
VDD Range
14.25/15.75
14.25/15.75
14.25/15.75
V min/max
V
SS Range
–14.25/–15.75 –14.25/–15.75 –14.25/–15.75 V min/max
Power Supply Rejection
∆Gain/∆VDD
∆Gain/∆VSS
IDD
0.01
0.01
0.01
0.01
0.01
0.01
% per % max
% per % max
mA max
VDD = 15 V 5%, VREF = –10 V
VSS = –15 V 5%, VREF = +10 V
Outputs Unloaded. Inputs at Thresholds.
Typically 5 mA
Outputs Unloaded. Inputs at Thresholds.
Typically 3 mA
8
6
8
6
8
6
ISS
mA max
AC CHARACTERISTICS2, 3
Voltage Output Settling Time
3
5
3
5
3
5
µs typ
µs max
Settling Time to Within 1/2 LSB of Final
Value. DAC Latch Alternately Loaded
with All 0s and All 1s
Slew Rate
Digital-to-Analog Glitch Impulse
Channel-to-Channel Isolation
11
10
11
10
11
10
V/µs typ
nV secs typ
1 LSB Change Around Major Carry
V
REFA to VOUTB
–95
–95
–90
750
175
–88
1
–95
–95
–90
750
175
–88
1
–95
–95
–90
750
175
–88
1
dB typ
VREFA = 20 V p-p, 10 kHz Sine Wave.
DAC Latches Loaded with All 0s
VREFB = 20 V p-p, 10 kHz Sine Wave.
DAC Latches Loaded with All 0s
VREF = 20 V p-p, 10 kHz Sine Wave.
DAC Latch Loaded with All 0s
VREF = 100 mV p-p Sine Wave. DAC
Latch Loaded with All 1s
VREF = 20 V p-p Sine Wave. DAC
Latch Loaded with All 1s
VREF = 6 V rms, 1 kHz. DAC Latch
Loaded with All 1s
VREFB to VOUTA
dB typ
Multiplying Feedthrough Error
Unity Gain Small Signal BW
Full Power BW
dB typ
kHz typ
kHz typ
dB typ
Total Harmonic Distortion
Digital Crosstalk
nV secs typ
Code Transition from All 0s to All 1s and
Vice Versa
Output Noise Voltage @ +25°C
(0.1 Hz to 10 Hz)
Digital Feedthrough
See Typical Performance Graphs
Amplifier Noise and Johnson Noise of RFB
2
1
2
1
2
1
µV rms typ
nV secs typ
NOTES
1Temperature ranges are as follows: A, B Versions, –40°C to +85°C; S Version, –55°C to +125°C.
2See Terminology.
3Guaranteed by design and characterization, not production tested.
4The Devices are functional with VDD/VSS
=
12 V (See typical performance graphs.).
Specifications subject to change without notice.
–2–
REV. C
ADI [ ADI ]
