AD1674
(for all grades TMIN to TMAX with V = +15 V ؎ 10% or +12 V ؎ 5%,
CC
V
LOGIC = +5 V ؎10%, V = –15 V ؎ 10% or –12 V ؎ 5%; V = 0.4 V,
EE IL
V = 2.4 V unless otherwise noted)
IH
SWITCHING SPECIFICATIONS
CO NVERTER START TIMING (Figur e 1)
J, K, A, B, Grades
T Grade
P aram eter
Sym bol Min Typ Max Min Typ Max Units
tHEC
tHSC
CE
Conversion T ime
8-Bit Cycle
12-Bit Cycle
__
CS
tC
tC
tDSC
tHEC
tSSC
7
9
8
10
200
7
9
8
10
225 ns
µs
µs
tSSC
ST S Delay from CE
CE Pulse Width
CS to CE Setup
CS Low During CE High tHSC
R/C to CE Setup tSRC
R/C Low During CE High tHRC
A0 to CE Setup tSAC
A0 Valid During CE High tHAC
_
R/C
tSRC tHRC
50
50
50
50
50
0
50
50
50
50
50
0
ns
ns
ns
ns
ns
ns
ns
tSAC
tHAC
A
0
tC
50
50
STS
tDSC
DB11 – DB0
HIGH IMPEDANCE
READ TIMING—FULL CO NTRO L MO D E ( Figur e 2)
J, K, A, B, Grades
T Grade
Figure 1. Converter Start Tim ing
P aram eter
Sym bol Min Typ Max Min Typ Max Units
1
Access T ime
Data Valid After CE Low tHD
tDD
75
150
150
75 150 ns
252
203
252
154
ns
ns
150 ns
CE
__
CS
5
tHSR
Output Float Delay
CS to CE Setup
R/C to CE Setup
A0 to CE Setup
tHL
tSSR
tSSR
tSRR
tSAR
50
0
50
0
50
0
50
0
ns
ns
ns
ns
ns
_
R/C
tSSR
tHRR
CS Valid After CE Low tHSR
R/C High After CE Low tHRR
0
0
A0 Valid After CE Low
tHAR
50
50
ns
A
0
tSAR
tHAR
NOT ES
1tDD is measured with the load circuit of Figure 3 and is defined as the time
required for an output to cross 0.4 V or 2.4 V.
tHS
STS
20°C to T MAX
3At –40°C.
4At –55°C.
.
tHD
HIGH
IMPEDANCE
HIGH
IMP.
5tHL is defined as the time required for the data lines to change 0.5 V when
loaded with the circuit of Figure 3.
DATA
VALID
DB11 – DB0
tDD
tHL
All min and max specifications are guaranteed.
Specifications subject to change without notice.
Figure 2. Read Tim ing
Test
VCP
CO UT
Access T ime High Z to Logic Low
Float T ime Logic High to High Z
Access T ime High Z to Logic High
Float T ime Logic Low to High Z
5 V
0 V
0 V
5 V
100 pF
10 pF
100 pF
10 pF
I
OL
D
OUT
V
CP
C
OUT
I
OH
Figure 3. Load Circuit for Bus Tim ing Specifications
REV. C
–5–
ADI [ ADI ]
