AD7874
TERMINO LO GY
P IN CO NFIGURATIO NS
D IP and SO IC
ACQ UISITIO N TIME
Acquisition T ime is the time required for the output of the
track/hold amplifiers to reach their final values, within ±1/2
LSB, after the falling edge of INT (the point at which the track/
holds return to track mode). T his includes switch delay time,
slewing time and settling time for a full-scale voltage change.
V
V
1
2
28
27
26
V
V
V
IN1
IN4
IN3
SS
IN2
V
3
DD
INT
CONVST
RD
4
25 REF OUT
24 REF IN
23 AGND
22 DB0 (LSB)
21 DB1
AP ERTURE D ELAY
Aperture Delay is defined as the time required by the internal
switches to disconnect the hold capacitors from the inputs. T his
produces an effective delay in sample timing. It is measured by
applying a step input and adjusting the CONVST input position
until the output code follows the step input change.
5
6
AD7874
TOP VIEW
(Not to Scale)
CS
7
CLK
8
V
9
20 DB2
DD
10
DB11 (MSB)
19 DB3
AP ERTURE D ELAY MATCH ING
Aperture Delay Matching is the maximum deviation in aperture
delays across the four on-chip track/hold amplifiers.
DB10 11
12
18 DB4
DB9
17 DB5
DB8 13
14
16 DB6
AP ERTURE JITTER
DGND
15 DB7
Aperture Jitter is the uncertainty in aperture delay caused by
internal noise and variation of switching thresholds with signal
level.
LCCC
D RO O P RATE
Droop Rate is the change in the held analog voltage resulting
from leakage currents.
4
3
2
28 27 26
1
25
24
23
5
6
CONVST
RD
REF OUT
REF IN
AGND
CH ANNEL-TO -CH ANNEL ISO LATIO N
7
CS
AD7874
TOP VIEW
(Not to Scale)
Channel-to-Channel Isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 1 kHz signal to the other three inputs. T he figure given is
the worst case across all four channels.
8
22 DB0 (LSB)
CLK
9
21
20
V
DB1
DB2
DD
10
11
DB11 (MSB)
DB10
19 DB3
SNR, TH D , IMD
12 13 14 15 16 17 18
See DYNAMIC SPECIFICAT IONS section.
–4–
REV. C
ADI [ ADI ]
