AD7874
MICRO P RO CESSO R INTERFACING
TIMER
T he AD7874 high speed bus timing allows direct interfacing to
DSP processors as well as modern 16-bit microprocessors.
Suitable microprocessor interfaces are shown in Figures 12
through 16.
PA2
PA0
ADDRESS BUS
ADDR
DECODE
CONVST
CS
AD 7874–AD SP -2100 Inter face
MEN
Figure 12 shows an interface between the AD7874 and the
ADSP-2100. Conversion is initiated using a timer which allows
very accurate control of the sampling instant on all four chan-
nels. T he AD7874 INT line provides an interrupt to the ADSP-
2100 when conversion is completed on all four channels. T he
four conversion results can then be read from the AD7874 using
four successive reads to the same memory address. T he follow-
ing instruction reads one of the four results (this instruction is
repeated four times to read all four results in sequence):
EN
AD7874*
TMS32010
INT
INT
RD
DEN
DB11
DB0
MR0 = DM(ADC)
D15
D0
DATA BUS
where MR0 is the ADSP-2100 MR0 register and
ADC is the AD7874 address.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. AD7874–TMS32010 Interface
AD 7874–TMS320C25 Inter face
DMA13
TIMER
ADDRESS BUS
DMA0
Figure 14 shows an interface between the AD7874 and the
T MS320C25. As with the two previous interfaces, conversion is
initiated with a timer and the processor is interrupted when the
conversion sequence is completed. T he T MS320C25 does not
have a separate RD output to drive the AD7874 RD input di-
rectly. T his has to be generated from the processor ST RB and
R/W outputs with the addition of some logic gates. T he RD sig-
nal is OR-gated with the MSC signal to provide the one WAIT
state required in the read cycle for correct interface timing.
Conversion results are read from the AD7874 using the follow-
ing instruction:
CONVST
ADDR
DECODE
CS
DMS
EN
AD7874*
ADSP-2100
(ADSP-2101/
ADSP-2102)
IRQn
INT
RD
DMRD (RD)
DB11
DB0
IN D,ADC
where D is Data Memory address and
ADC is the AD7874 address.
DMD15
DMD0
DATA BUS
* ADDITIONAL PINS OMITTED FOR CLARITY
TIMER
A15
ADDRESS BUS
Figure 12. AD7874–ADSP-2100 Interface
A0
AD 7874–AD SP -2101/AD SP -2102 Inter face
T he interface outlined in Figure 12 also forms the basis for an
interface between the AD7874 and the ADSP-2101/ADSP-2102.
T he READ line of the ADSP-2101/ADSP-2102 is labeled RD.
In this interface, the RD pulse width of the processor can be
programmed using the Data Memory Wait State Control Regis-
ter. T he instruction used to read one of the four results is as
outlined for the ADSP-2100.
ADDR
CONVST
DECODE
CS
IS
EN
AD7874*
TMS320C25
INTn
INT
STRB
R/W
RD
AD 7874–TMS32010 Inter face
An interface between the AD7874 and the T MS32010 is shown
in Figure 13. Once again the conversion is initiated using an ex-
ternal timer and the T MS32010 is interrupted when all four
conversions have been completed. T he following instruction is
used to read the conversion results from the AD7874:
READY
MSC
DB11
DB0
D15
D0
IN D,ADC
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
where D is Data Memory address and
ADC is the AD7874 address.
Figure 14. AD7874–TMS320C25 Interface
–10–
REV. C
ADI [ ADI ]
