AD7874
(V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND = O V, tCLK = 2.5 MHz external unless
otherwise noted.)
DD
SS
1
TIMING CHARACTERISTICS
P aram eter
A, B Versions
S Version
Units
Conditions/Com m ents
t1
t2
t3
t4
t5
50
0
60
0
50
0
70
0
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
µs min
µs max
µs min
µs max
µs max
CONVST Pulse Width
CS to RD Setup T ime
RD Pulse Width
CS to RD Hold T ime
RD to INT Delay
60
57
5
45
130
31
32.5
31
35
10
60
70
5
50
150
31
32.5
31
35
10
2
t6
t7
Data Access T ime after RD
Bus Relinquish T ime after RD
3
t8
tCONV
Delay T ime between Reads
CONVST to INT, External Clock
CONVST to INT, External Clock
CONVST to INT, Internal Clock
CONVST to INT, Internal Clock
Minimum Input Clock Period
tCLK
NOT ES
1T iming Specifications in bold pr int are 100% production tested. All other times are sample tested at +25 °C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. T he measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. T his means that the time, t 7, quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
ABSO LUTE MAXIMUM RATINGS*
(T A = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
TO OUTPUT
+2.1V
PIN
50pF
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating T emperature Range
200µA
Figure 1. Load Circuit for Access Tim e
1.6mA
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . 1,000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
TO OUTPUT
+2.1V
PIN
50pF
200µA
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Figure 2. Load Circuit for Bus Relinquish Tim e
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7874 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–
ADI [ ADI ]
