AD2S80A
Parameter
Conditions
Min
Typ
Max
Unit
DATA LOAD
Sense
Internally Pulled High (100 kΩ)
to VS. Logic LO Allows
150
300
ns
Data to be Loaded into the
Counters from the Data Lines
BUSY3
Sense
Logic HI When Position O/P
Changing
Width
Load
200
600
1
ns
LSTTL
Use Additional Pull-Up
DIRECTION3
Sense
Logic HI Counting Up
Logic LO Counting Down
Max Load
3
LSTTL
RIPPLE CLOCK3
Sense
Logic HI
All 1s to All 0s
All 0s to All 1s
Dependent on Input Velocity
Before Next Busy
Width
Reset
Load
300
2.0
3
LSTTL
V
DIGITAL INPUTS
High Voltage, VIH
INHIBIT, ENABLE
DB1–DB16, Byte Select
VS = 10.8 V, VL = 5.0 V
INHIBIT, ENABLE
Low Voltage, VIL
0.8
V
DB1–DB16, Byte Select
VS = 13.2 V, VL = 5.0 V
DIGITAL INPUTS
High Current, IIH
INHIBIT, ENABLE
DB1–DB16
VS = 13.2 V , VL = 5.5 V
INHIBIT, ENABLE
DB1–DB16, Byte Select
VS = 13.2 V, VL = 5.5 V
؎100
؎100
µA
µA
Low Current, IIL
DIGITAL INPUTS
Low Voltage, VIL
ENABLE = HI
1.0
V
SC1, SC2, Data Load
VS = 12.0 V, VL = 5.0 V
ENABLE = HI
SC1, SC2, Data Load
VS = 12.0 V, VL = 5.0 V
Low Current, IIL
–400
µA
DIGITAL OUTPUTS
High Voltage, VOH
DB1–DB16
2.4
V
V
RIPPLE CLK, DIR
VS = 12.0 V, VL = 4.5 V
IOH = 100 µA
Low Voltage, VOL
DB1–DB16
0.4
RIPPLE CLK, DIR
VS = 12.0 V, VL = 5.5 V
IOL = 1.2 mA
THREE-STATE LEAKAGE
Current IL
DB1–DB16 Only
VS = 12.0 V, VL = 5.5 V
VOL = 0 V
VS = 12.0 V, VL = 5.5 V
VOH = 5.0 V
100
100
µA
µA
NOTES
1Refer to small signal bandwidth.
2Output offset dependent on value for R6.
3Refer to timing diagram.
Specifications subject to change without notice.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
REV. B
–3–
ADI [ ADI ]
