AD7224
Table I. AD 7224 Truth Table
a +2.5 V bandgap reference and the AD584, a precision +10 V
reference. Note that in order to achieve an output voltage range
of 0 V to +10 V, a nominal +15 V ± 5% power supply voltage is
required by the AD7224.
RESET LDAC WR CS Function
H
H
H
H
H
H
H
L
L
L
H
X
L
g
L
g
X
L
Both Registers are T ransparent
Both Registers are Latched
Both Registers are Latched
Input Register T ransparent
Input Register Latched
DAC Register T ransparent
DAC Register Latched
Both Registers Loaded
X
H
H
H
L
X
H
L
GRO UND MANAGEMENT
AC or transient voltages between AGND and DGND can cause
noise at the analog output. T his is especially true in micropro-
cessor systems where digital noise is prevalent. T he simplest
method of ensuring that voltages at AGND and DGND are
equal is to tie AGND and DGND together at the AD7224. In
more complex systems where the AGND and DGND intertie is
on the backplane, it is recommended that two diodes be con-
nected in inverse parallel between the AD7224 AGND and
DGND pins (IN914 or equivalent).
L
H
H
X
L
X
With All Zeros
g
g
H
L
H
L
H
L
Both Register Latched With All Zeros
and Output Remains at Zero
Both Registers are T ransparent and
Output Follows Input Data
H = High State, L = Low State, X = Don’t Care.
All control inputs are level triggered.
Applying the AD7224
T he contents of both registers are reset by a low level on the
RESET line. With both registers transparent, the RESET line
functions like a zero override with the output brought to 0 V for
the duration of the RESET pulse. If both registers are latched, a
“LOW” pulse on RESET will latch all 0s into the registers and
the output remains at 0 V after the RESET line has returned
“HIGH”. T he RESET line can be used to ensure power-up to
0 V on the AD7224 output and is also useful, when used as a
zero override, in system calibration cycles. Figure 3 shows the
input control logic for the AD7224.
UNIP O LAR O UTP UT O P ERATIO N
T his is the basic mode of operation for the AD7224, with the
output voltage having the same positive polarity as VREF. T he
AD7224 can be operated single supply (VSS = AGND) or with
positive/negative supplies (see op-amp section which outlines
the advantages of having negative VSS). Connections for the uni-
polar output operation are shown in Figure 5. T he voltage at
VREF must never be negative with respect to DGND. Failure to
observe this precaution may cause parasitic transistor action and
possible device destruction. T he code table for unipolar output
operation is shown in T able II.
LDAC
DAC
REGISTER
V
V
DD
WR
REF
3
INPUT
REGISTER
DB7
CS
DATA
RESET
(8-BIT)
INPUT DATA
DB0
CS
V
DAC
OUT
Figure 3. Input Control Logic
WR
t
LDAC
RESET
1
AD7224
CS
t
t
4
3
t
t
2
2
WR
AGND
DGND
V
SS
t
t
4
3
t
1
LDAC
t
6
t
5
Figure 5. Unipolar Output Circuit
DATA
IN
DATA
VALID
Table III. Unipolar Code Table
NOTES:
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF V
.
DD
D AC Register Contents
t
= t = 20ns OVER V
RANGE
DD
r
f
V
+ V
2
INH
INL
MSB
LSB
Analog O utput
2. TIMING MEASUREMENT REFERENCE LEVEL IS
255
+VREF
Figure 4. Write Cycle Tim ing Diagram
1 1 1 1
1 1 1 1
256
129
+VREF
SP ECIFICATIO N RANGES
1 0 0 0
0 0 0 1
256
For the DAC to maintain specified accuracy, the reference volt-
age must be at least 4 V below the VDD power supply voltage.
T his voltage differential is required for correct generation of bias
voltages for the DAC switches.
128
256
VREF
2
+VREF
+VREF
+VREF
= +
1 0 0 0
0 1 1 1
0 0 0 0
1 1 1 1
127
256
With dual supply operation, the AD7224 has an extended VDD
range from +12 V ± 5% to +15 V ± 10% (i.e., from +11.4 V to
+16.5 V). Operation is also specified for a single VDD power
supply of +15 V ± 5%.
1
256
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
0 V
Performance is specified over a wide range of reference voltages
from 2 V to (VDD – 4 V) with dual supplies. T his allows a range
of standard reference generators to be used such as the AD580,
1
256
Note: 1 LSB = V
2−8 = V
(
)
(
)
REF
REF
–6–
REV. B
ADI [ ADI ]
