AD526
TIMING AND CONTROL
Table I. Logic Input Truth Table
DIGITAL FEEDTHROUGH
With either CS or CLK or both held high, the AD526 gain state
will remain constant regardless of the transitions at the A0, A1,
A2 or B inputs. However, high speed logic transitions will un-
avoidably feed through to the analog circuitry within the AD526
causing spikes to occur at the signal output.
Gain Code
Control
Condition
Gain
A2 A1 A0 B CLK (CS = 0)
Condition
X
0
0
0
0
1
X
X
0
0
0
0
1
X
0
0
1
1
X
X
X
0
0
1
X
0
1
0
1
X
X
X
0
1
0
X
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
Previous State Latched
This feedthrough effect can be completely eliminated by operat-
ing the AD526 in the transparent mode and latching the gain
code in an external bank of latches (Figure 36).
1
2
4
8
16
1
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Latched
To operate the AD526 using serial inputs, the configuration
shown in Figure 36 can be used with the 74LS174 replaced by a
serial-in/parallel-out latch, such as the 54LS594.
1
A1
A0
A2
B
+5V
1
Latched
2
4
Latched
Latched
1F
TIMING
SIGNAL
74LS174
1
X
1
X
8
Latched
16
Latched
+V
S
NOTE: X = Don’t Care.
0.1F
The specifications on page 3, in combination with Figure 35,
give the timing requirements for loading new gain codes.
OUT
FORCE
9
16
15
14
13
12
11
B
10
A1 A0
CS CLK A2
LOGIC AND LATCHES
GAIN CODE
VALID DATA
INPUTS
16
8
4
2
1
T
C
V
OUT
GAIN NETWORK
CLK OR CS
–
+
T
T
H
S
AD526
T
T
T
= MINIMUM CLOCK CYCLE NOTE: THRESHOLD LEVEL FOR
C
S
H
1
2
3
4
5
6
7
8
OUT
SENSE
GAIN CODE, CS, AND CLK IS 1.4V.
= DATA SETUP TIME
= DATA HOLD TIME
0.1F
V
IN
Figure 35. AD526 Timing
–V
S
Figure 36. Using an External Latch to Minimize Digital
Feedthrough
–9–
REV. D
ADI [ ADI ]
