ADG526A/ADG527A
TIMING
Figure 13 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
Figure 14 shows the reset pulse width, tRS, and reset turn-off
RS
time, tOFF
(
).
WR
therefore, while
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of
is held low, the latches are transparent and
Note that all digital input signal rise and fall times are measured
from 10% to 90% of 3 V, tR = tF = 20 ns.
WR
.
3V
3V
RS
0V
1.5V
WR
0V
1.5V
tRS
tOFF (RS)
tW
tS
tH
V
O
3V
EN, A0, A1,
A2, (A3)
0V
0.8V
2.0V
SWITCH
OUTPUT
0V
0.8V
Figure 13. Timing Sequence
Figure 14. Reset Pulse
Rev. C | Page 13 of 20
ADI [ ADI ]
