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5962-89710013A 参数 Datasheet PDF下载

5962-89710013A图片预览
型号: 5962-89710013A
PDF下载: 下载PDF文件 查看货源
内容描述: 锁存CMOS 8位/ 16通道模拟多路复用器 [CMOS Latched 8-/16-Channel Analog Multiplexers]
分类和应用: 复用器开关复用器或开关信号电路
文件页数/大小: 20 页 / 415 K
品牌: ADI [ ADI ]
 浏览型号5962-89710013A的Datasheet PDF文件第5页浏览型号5962-89710013A的Datasheet PDF文件第6页浏览型号5962-89710013A的Datasheet PDF文件第7页浏览型号5962-89710013A的Datasheet PDF文件第8页浏览型号5962-89710013A的Datasheet PDF文件第10页浏览型号5962-89710013A的Datasheet PDF文件第11页浏览型号5962-89710013A的Datasheet PDF文件第12页浏览型号5962-89710013A的Datasheet PDF文件第13页  
ADG526A/ADG527A  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
DA  
V
DD  
DB  
RS  
SS  
4
3
2
1
28 27 26  
3
S8A  
S7A  
S6A  
S5A  
S4A  
S3A  
S2A  
S1A  
EN  
PIN 1  
5
6
25  
S7A  
S7B  
S6B  
S5B  
S4B  
S3B  
S2B  
4
S8B  
S7B  
S6B  
S5B  
S4B  
S3B  
S2B  
S1B  
GND  
WR  
IDENTFIER  
5
24 S6A  
ADG527A  
6
23  
7
S5A  
TOP VIEW  
ADG527A  
TOP VIEW  
7
(Not to Scale)  
22  
8
S4A  
8
(Not to Scale)  
21  
20  
9
S3A  
S2A  
9
10  
10  
11  
12  
13  
14  
S1B 11  
19 S1A  
A0  
12 13 14 15 16 17 18  
NC = NO CONNECT  
A1  
NC  
A2  
NC = NO CONNECT  
Figure 5. ADG527A PDIP, SOIC Pin Configuration  
Figure 6. ADG527A PLCC Pin Configuration  
Table 5. ADG527A Pin Function Descriptions  
Pin No. Mnemonic  
Description  
1
2
VDD  
DB  
Most Positive Power Supply Potential.  
Drain Terminal. This pin can be an input or output.  
3
RS  
Reset. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off).  
Source Terminal. This pin can be an input or output.  
Source Terminal. This pin can be an input or output.  
Source Terminal. This pin can be an input or output.  
Source Terminal. This pin can be an input or output.  
Source Terminal. This pin can be an input or output.  
Source Terminal. This pin can be an input or output.  
Source Terminal. This pin can be an input or output.  
Source Terminal. This pin can be an input or output.  
Ground (0 V) Reference.  
Write. The WR signal latches the state of the address control lines and the enable line.  
No Connect.  
Logic Control Inputs. Selects which source terminal is connected to the drain (D).  
Logic Control Inputs. Selects which source terminal is connected to the drain (D).  
Logic Control Inputs. Selects which source terminal is connected to the drain (D).  
Enable. Active high logic control input.  
Source Terminal. This pin can be an input or output.  
Source Terminal. This pin can be an input or output.  
Source Terminal. This pin can be an input or output.  
Source Terminal. This pin can be an input or output.  
Source Terminal. This pin can be an input or output.  
Source Terminal. This pin can be an input or output.  
Source Terminal. This pin can be an input or output.  
Source Terminal. This pin can be an input or output.  
Most Negative Power Supply Potential.  
4
5
6
7
8
9
S8B  
S7B  
S6B  
S5B  
S4B  
S3B  
S2B  
S1B  
GND  
WR  
NC  
A2  
A1  
A0  
EN  
S1A  
S2A  
S3A  
S4A  
S5A  
S6A  
S7A  
S8A  
VSS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
DA  
Drain Terminal. This pin can be an input or output.  
Rev. C | Page 9 of 20