AD7846
TIMING CHARACTERISTICS
VDD = +14.25 V to +15.75 V, VSS = −14.25 V to −15.75 V, VCC = +4.75 V to +5.25 V, unless otherwise noted.
Table 3.
Parameter1
ꢀimit at TMIN to TMAX (All Versions)
Unit
Test Conditions/Comments
R/W to CS setup time
CS pulse width (write cycle)
R/W to CS hold time
Data setup time
Data hold time
Data access time
0
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
t1
t2
t3
t4
t5
60
0
60
0
120
10
60
0
2
t6
t7
3
Bus relinquish time
CLR setup time
t±
70
0
CLR pulse width
t9
CLR hold time
t10
t11
t12
70
130
LDAC pulse width
CS pulse width (read cycle)
1 Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a
voltage level of 1.6 V.
2 t6 is measured with the load circuits of Figure 3 and Figure 4 and defined as the time required for an output to cross 0.± V or 2.4 V.
3 t7 is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 5 and Figure 6.
t1
t3
t1
t3
5V
0V
5V
0V
5V
0V
5V
0V
5V
0V
R/W
CS
t12
t2
t5
t7
t6
t4
DB0
TO
DB15
DATA VALID
DATA VALID
t9
t10
t8
t9
t10
t8
CLR
t11
LDAC
Figure 2. Timing Diagram
DBn
DBn
100pF
10pF
3kΩ
DGND
3kΩ
DGND
Figure 3. Load Circuit for Access Time (t6)—High Z to VOH
Figure 5. Load Circuit for Access Time (t7)—High Z to VOH
5V
5V
3kΩ
3kΩ
DBn
DBn
10pF
100pF
DGND
DGND
Figure 6. Load Circuits for Bus Relinquish Time (t7)—High Z to VOL
Figure 4. Load Circuits for Bus Relinquish Time (t6)—High Z to VOL
Rev. G | Page 5 of 24
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