AD7821
TIMING CHARACTERISTICS1 (VDD = +5 V ؎ 5%, VSS = 0 V or –5 V ؎ 5%; Unipolar or Bipolar Input Range)
Limit at
TMIN, TMAX
(K, B Versions)
Limit at
TMIN, TMAX
(T Version)
Limit at +25؇C
(All Versions)
Parameter
Unit
Conditions/Comments
tCSS
tCSH
tRDY
0
0
70
0
0
85
0
0
100
ns min
ns min
ns max
CS to RD/WR Setup Time
CS to RD/WR Hold Time
CS to RDY Delay. Pull-Up
Resistor 5 kΩ
2
tCRD
tACC0
700
875
975
ns max
Conversion Time (RD Mode)
Data Access Time (RD Mode)
CL = 20 pF
3
tCRD + 25
tCRD + 50
50
tCRD + 30
tCRD + 65
–
tCRD + 35
tCRD + 75
–
ns max
ns max
ns typ
CL = 100 pF
RD to INT Delay (RD Mode)
2
tINTH
80
15
60
350
250
10
250
160
85
15
70
425
325
10
350
205
90
15
80
500
400
10
450
240
ns max
ns min
ns max
ns min
ns min
µs max
ns min
ns min
4
tDH
Data Hold Time
tP
tWR
Delay Time Between Conversions
Write Pulsewidth
tRD
Delay Time between WR and RD Pulses
RD Pulsewidth (WR-RD Mode, see Figure 12b)
Determined by tACC1
Data Access Time (WR-RD Mode, see Figure 12b)
CL = 20 pF
CL = 100 pF
RD to INT Delay
tREAD1
3
tACC1
160
185
150
380
500
65
205
235
185
–
610
75
240
275
220
–
700
85
ns max
ns max
ns max
ns typ
ns max
ns min
tRI
2
tINTL
WR to INT Delay
tREAD2
RD Pulsewidth (WR-RD Mode, see Figure 12a)
Determined by tACC2
Data Access Time (WR-RD Mode, see Figure 12a)
CL = 20 pF
CL = 100 pF
WR to INT Delay (Stand-Alone Operation)
Data Access Time after INT
(Stand-Alone Operation)
3
tACC2
65
90
80
75
110
100
85
130
120
ns max
ns max
ns max
2
tIHWR
3
tID
30
45
35
60
40
70
ns max
ns max
CL = 20 pF
CL = 100 pF
NOTES
1Sample tested at +25°C to ensure compliance. All input control signals are specified with tRISE = tFALL = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2CL = 50 pF.
3Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
ORDERING GUIDE
Test Circuits
Total
Temperature
Range
Unadjusted Package
Model1
Error (LSB) Option2
AD7821KN –40°C to +85°C
AD7821KP –40°C to +85°C
AD7821KR –40°C to +85°C
AD7821BQ –40°C to +85°C
AD7821TQ –55°C to +125°C
AD7821TE –55°C to +125°C
1 max
1 max
1 max
1 max
1 max
1 max
N-20
P-20A
RW-20
Q-20
Q-20
E-20A
a. High Z to VOH
b. High Z to VOL
Figure 1. Load Circuits for Data Access Time Test
NOTES
1To order MIL-STD-883, Class B processed parts, add /883B to part
number. Contact local sales office for military data sheet.
2E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded
Chip Carrier; Q = Cerdip; R = SOIC.
a. VOH to High Z
b. VOL to High Z
Figure 2. Load Circuits for Data Hold Time Test
REV. B
–3–
ADI [ ADI ]
